Datasheet

32
9596A–AT42–10/10
AT42QT1070
Figure A-3. START and STOP Conditions
A.4 Address Byte Format
All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and
an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a
write operation is performed. When the device recognizes that it is being addressed, it will
acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address byte consisting of a
slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host
must be consistent with that selected with the option jumpers.
Figure A-4. Address Byte Format
A.5 Data Byte Format
All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data
transfer, the host generates the clock and the START and STOP conditions, while the Receiver
is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the
Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line
high, a NACK is signaled.
SDA
SCL
START STOP
SDA
SCL
Addr MSB Addr LSB R/W ACK
START
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