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WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
t
H
WRT
CMD5
WRT
CMD0
DATA
217B
DATA
1B
DATA
0B
DATA
2B
1 2 6
t
WL
222 223 224
1 2 3 4 5 6 7 8 9
t
D6
(2)
t
WH
WriteCommand(6Bits)
DATA
217C
DATA
216C
DATA
215C
WRT
CMD4
WriteData(218Bits)
DATA
0A
WRT
CMD5
WRT
CMD4
WRT
CMD0
WRT
CMD5
WRT
CMD1
WRT
CMD0
DATA
0A
DATA
217B
DATA
2B
DATA
1B
DATA
0B
DATA
1A
DATA
0A
DATA
3B
DATA
2B
DATA
1B
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD5
WRT
CMD4
WRT
CMD2
DATA
217A
DATA
216A
DATA
1A
DATA
0A
DATA
216A
DATA
215A
DATA
0A
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
DATA
217C
DATA
216C
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
DATA
217C
WRT
CMD4
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
DATA
217B
DATA
216B
DATA
215B
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
DATA
217B
DATA
216B
DATA
215B
DATA
214B
DATA
0B
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD5
WRT
CMD4
WRT
CMD3
WRT
CMD2
WRT
CMD1
WRT
CMD0
DATA
217B
DATA
216B
DATA
215B
DATA
217A
DATA
216A
DATA
1A
DATA
0A
t /t
R0 F0
t
D0
SDTI
SDTO
SCKI
SCKO
t
W(SCKO)
LatchSignal
(Internal)
224-BitShift Register
LSB(Internal)
224-BitShiftRegister
LSB+1(Internal)
224-BitShiftRegister
MSB 1(Internal)-
224-BitShift Register
MSB(Internal)
LatchData
(Internal)
PreviousData
LatestData (AllGSDataare0001h)
t
D1
BLANKBitin DataLatch
(Internal)
1
0
EXTGCKBitinDataLatch
(Internal)
0
1
OUTTMGBitin DataLatch
(Internal)
0
1
t
D5
t
D4
t
D3
OUTR0-R3
ON
OFF
t
F1
(V )
OUTXnH
(V
OUTXnL
(1)
)
ON
OFF
(V )
OUTXnH
(V
OUTXnL
)
(1)
ON
OFF
(V )
OUTXnH
(V
OUTXnL
)
(1)
t
R1
OUTG0-G3
OUTB0-B3
t
SU
¼
¼
¼
¼
TLC59711
www.ti.com
SBVS181A –OCTOBER 2011–REVISED JULY 2012
(1) OUTXn on-off timing depends on previous GS data in the 218-bit data latch.
(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal latch signal
generation.
Figure 9. Data Write and OUTXn Switching Timing (OUTTMG = 1)
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