Datasheet

6-BitWrite
Command
Decoder
SDTO
SCKI
SDTI
ToGStiming controlcircu t.iTothethreegroupsof7-bitBC,
PWMtimingcontrol,GSclockcounter,
andclockselectcircuit.
224-BitShiftRegister
LSB
MSB
Write
Command
Bit5
218
Write
Data
Bit3
218-BitData Latch
0123215216217218
223
LSB
0
12
3
OUTR0
Bit3
OUT
TMG
215
217
MSB
19226
214
6
WriteCommand=25h(100101b)
Inte nalr
LatchPulse
Theinternallatchpulseisgenerated
aftereightperiodsbetweenthelast
2SCKIrisingedgeswithnoinput.
216 214
EXT
GCK
TMG
RST
DSP
RPT
¼ ¼
¼
Write
Command
Bit0
Write
Data
Bit217
Write
Data
Bit216
Write
Data
Bit215
Write
Data
Bit214
Write
Data
Bit2
Write
Data
Bit1
Write
Data
Bit0
OUTR0
Bit2
OUTR0
Bit1
OUTR0
Bit0
TLC59711
SBVS181A –OCTOBER 2011–REVISED JULY 2012 www.ti.com
REGISTER AND DATA LATCH CONFIGURATION
The TLC59711 has a 224-bit shift register and a 218-bit data latch that set grayscale (GS) data, global
brightness control (BC), and function control (FC) data into the device. When the internal latch pulse is generated
and the data of the six MSBs in the shift register are 25h, the 218 following data bits in the shift register are
copied into the 218-bit data latch. If the data of the six MSBs is not 25h, the 218 data bits are not copied into the
218-bit data latch. The data in the data latch are used for GS, BC, and FC functions. Figure 23 shows the shift
register and the data latch configuration.
Figure 23. Common Shift Register and Control Data Latch Configuration
224-Bit Shift Register
The 224-bit shift register is used to input data from the SDTI pin with the SCKI clock into the TLC59711. The
shifted data in this register is used for GS, BC, and FC. The six MSBs are used for the write command. The LSB
of the register is connected to the SDTI pin and the MSB is connected to the SDTO pin. On each SCKI rising
edge, the data on SDTI are shifted into the register LSB and all 224 bits are shifted towards the MSB. The
register MSB is always connected to SDTO. When the device is powered up, the data in the 224-bit shift register
is not set to any default value.
218-Bit Data Latch
The 218-bit data latch is used to latch the GS, BC, and FC data. The 218 LSBs in the 244-bit shift register are
copied to the data latch when the internal latch pulse is generated with the 6-bit write command, 25h (100101b).
When the device is powered up, the data in the latch are not reset except for BLANK (bit 213) which is set to '1'
to force all outputs off. Therefore, GS, BC, and FC data must be set to the proper values before BLANK is set to
'0'. The 218-bit data latch configuration is shown in Figure 24 and the data bit assignment is shown in Table 5.
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