Datasheet

218-BitDataLatch
21
OUTTMG
1=
RisingEdge
MSB
217
¼
EXTCLK
1=
External
216
TMGRST
1=
Reset
215
DSPRPT
1=
Repeat
214
BLANK
1=
Blank
213
BCData
Bits6-0
forBLUE
212-206
BCData
Bits6-0
forGREEN
205-199
BCData
Bits6-0
forRED
198-192
OUTB3
Bit15
191
OUTB3
Bit0
176
OUTG0
Bit0
16
OUTR0
Bit15
15
OUTG0
Bit15
31
¼
OUTR0
Bit0
¼
LSB
0
218
FromLSB-sideof224-bitshiftregister.
5 192
Tofunctioncontrol(FC)circuit. Toglobalbrightnesscontrol(BC)circuit. Tograyscaletimingcontrol(GS)circuit.
FunctionControlData(5Bits) BCDataforOUTRn/Gn/Bn
(7Bits 3=21Bits)´
¼
GSDataforOUTG0
(16Bits)
GSDataforOUTB3
(16Bits)
GSDataforOUTR0
(16Bits)
TLC59711
www.ti.com SBVS181A –OCTOBER 2011–REVISED JULY 2012
Figure 24. 218-Bit Data Latch Configuration
Table 5. Data Latch Bit Assignment
BIT NUMBER BIT NAME CONTROLLED CHANNEL/FUNCTIONS
15-0 GSR0 GS data bits 15 to 0 for OUTR0
31-16 GSG0 GS data bits 15 to 0 for OUTG0
47-32 GSB0 GS data bits 15 to 0 for OUTB0
63-48 GSR1 GS data bits 15 to 0 for OUTR1
79-64 GSG1 GS data bits 15 to 0 for OUTG1
95-80 GSB1 GS data bits 15 to 0 for OUTB1
111-96 GSR2 GS data bits 15 to 0 for OUTR2
127-112 GSG2 GS data bits 15 to 0 for OUTG2
143-128 GSB2 GS data bits 15 to 0 for OUTB2
159-144 GSR3 GS data bits 15 to 0 for OUTR3
175-160 GSG3 GS data bits 15 to 0 for OUTG3
191-176 GSB3 GS data bits 15 to 0 for OUTB3
198-192 BCR BC data bits 6 to 0 for OUTR0-3
205-199 BCG BC data bits 6 to 0 for OUTG0-3
212-206 BCB BC data bits 6 to 0 for OUTB0-3
Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank).
When this bit is '0', all constant-current outputs (OUTR0-OUTB3) are controlled by the GS PWM timing
213 BLANK
controller. When this bit is '1', all constant-current outputs are forced off. The GS counter is reset to '0',
and the GS PWM timing controller is initialized. When the IC is powered on, this bit is set to '1'.
Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is '0', the auto repeat function is disabled. Each constant-current output is only turned on
214 DSPRPT once, according the GS data after BLANK is set to '0' or after the internal latch pulse is generated with
the TMGRST bit set to '1'. When this bit is '1', each output turns on and off according to the GS data
every 65536 GS reference clocks.
Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is '1', the GS counter is reset to '0' and all constant-current outputs are forced off when
the internal latch pulse is generated for data latching. This function is the same when BLANK is set to
215 TMGRST
'0'. Therefore, BLANK does not need to be controlled by an external controller when this mode is
enabled. When this bit is '0', the GS counter is not reset and no output is forced off even if the internal
latch pulse is generated.
GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock).
216 EXTGCK When this bit is '1', PWM timing refers to the SCKI clock. When this bit is '0', PWM timing refers to the
internal oscillator clock.
GS reference clock edge select bit for OUTXn on-off timing control in FC data (0 = falling edge, 1 =
rising edge).
217 OUTTMG
When this bit is '1', OUTXn are turned on or off at the rising edge of the selected GS reference clock.
When this bit is '0', OUTXn are turned on or off at the falling edge of the selected clock.
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