Datasheet

1
2
3
GS Reference Clock
(SCKI or Internal Oscillator)
OUTXn
(GSDATA = FFFFh)
OUTn is forced off
when BLANK is ‘1’.
Display period is repeated
by auto refresh function.
OFF
ON
OUTn is not turned
on until the next
BLANK changes
to ‘0’.
DSPRPT = 0
(Auto Repeat Off)
BLANK Bit
in Data Latch
(Internal)
DSPRPT Bit
in Data Latch
(Internal)
2nd Display Period
3rd Display Period
1st Display Period
1st
Display Period
4
5
65533
65534
65535
65536
1
2
3
4
5
65533
65534
65535
65536
1
2
3
4
5
6
7
8
9
10 1 65534
2 65535
65536
1
2
DSPRPT = 1
(Auto Repeat On)
218-bit dataare copied from shiftregister
when theinternallatch is generated.
N 3-
SCKI
1
Latch Pulse
(Internal)
PeriodA
Theinternallatch pulseis generatedwhen theSCKI risingedge is not input during 8 times of
Period Aifthe6-bit data of the MSB-side inthe244-bit shift register is the command code .25h
Thenext SCKIclock should start after8ormore
clockperiods(1.34 s,min) of the internal clock
fromthe internal latchpulsegeneration timing.
m
224-BitShift
RegisterData
(Internal)
218-Bit
Data Latch
(Internal)
Write command25h +218-bit data.
N 2- N 1- N
2 3 4 ¼
TLC59711
SBVS181A –OCTOBER 2011–REVISED JULY 2012 www.ti.com
INTERNAL LATCH PULSE GENERATION TIMING
The internal latch pulse is generated when the SCKI rising edge does not change for 8x the period between the
last SCKI rising edge and the second to last SCKI rising edge if the data of the six MSBs in the 244-bit shift
register are the command code 25h. The generation timing changes as a result of the SCKI frequency with the
time range between 16384 times the internal oscillator period (2.74ms), maximum, and 8x the internal oscillator
period (666 ns), minimum. Figure 25 shows the internal latch pulse generation timing.
Figure 25. Data Latch Pulse Generation Timing
AUTO DISPLAY REPEAT FUNCTION
This function repeats the total display period without a BLANK bit change, as long as the GS reference clock is
available. This function can be enabled or disabled with DSPRPT (bit 214) in the data latch. When the DSPRPT
bit is '1', this function is enabled and the entire display period repeats without a BLANK bit data change. When
the DSPRPT bit is '0', this function is disabled and the entire display period executes only once after the BLANK
bit is set to '0' or the internal latch pulse is generated when the display timing reset function is enabled. Figure 26
shows the auto display repeat operation timing.
Figure 26. Auto Repeat Display Function
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