Datasheet

IREF
GND
OUTR0
OUTG0
OUTB0
OUTR1
OUTG1
OUTB1
SDTI
SCKI
VREG
VCC
OUTB3
OUTG3
OUTR3
OUTB2
OUTG2
OUTR2
SDTO
SCKO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PowerPAD
(BottomSide)
TLC59711
SBVS181A –OCTOBER 2011–REVISED JULY 2012 www.ti.com
PIN CONFIGURATIONS
PWP PACKAGE
HTSSOP-20 PowerPAD
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME PWP I/O DESCRIPTION
Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-current
IREF 1 I/O
output. When this terminal is directly connected to GND, all outputs are forced off. The external resistor
should be placed close to the device.
GND 2 — Power ground terminal
OUTB0 5 O
BLUE constant-current outputs.
OUTB1 8 O
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTB2 15 O
Different voltages can be applied to each output.
OUTB3 18 O
OUTG0 4 O
GREEN constant-current outputs.
OUTG1 7 O
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTG2 14 O
Different voltages can be applied to each output.
OUTG3 17 O
OUTR0 3 O
RED constant-current outputs.
OUTR1 6 O
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTR2 13 O
Different voltages can be applied to each output.
OUTR3 16 O
Serial data shift clock input.
Data present on SDTI are shifted to the LSB of the 224-bit shift register with the SCKI rising edge Data in
SCKI 10 I
the shift register are shifted toward the MSB at each SCKI rising edge.
The MSB data of the shift register appear on SDTO.
Serial data shift clock output.
SCKO 11 O The input shift clock signal from SCKI is adjusted to the timing of the serial data output for SDTO and the
signal is then output at SCKO.
SDTI 9 I Serial data input for the 224-bit shift register
Serial data output of the 224-bit shift register.
SDTO 12 O SDTO is connected to the MSB of the 224-bit shift register. Data are clocked out at the falling edge
SCKO.
Internal linear voltage regulator output.
A decoupling capacitor of 1 µF must be connected. This output can be used for external devices as a 3.3-
VREG 20 I/O V power supply. This terminal can be connected with the VREG terminal of other devices to increase the
supply current. Also, this pin can be supplied with 3 V to 5.5 V from an external power supply by
connecting it to VCC.
VCC 19 — Power-supply terminal
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