Datasheet

VREG
IREF
GND
VCC
R
IREF
C
VREG
VCC
V
OUTXn
V
OUTfix
OUTR0
OUTXn
(1)
OUTB3
¼
¼
VREG
SDTO/SCKO
C
L
(1)
GND
VCC
C
VREG
VCC
VREG
OUTXn
(1)
C
L
(2)
R
L
IREF
GND
VCC
R
IREF
C
VREG
VCC
VLED
OUTXn
(1)
GND
VREG
OUTPUT
GND
VREG
INPUT
GND
TLC59711
www.ti.com SBVS181A –OCTOBER 2011–REVISED JULY 2012
PARAMETRIC MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT/OUTPUT SCHEMATICS
Figure 1. SDTI/SCKI
Figure 2. SDTO/SCKO
(1) X = R/G/B, n = 0-3.
Figure 3. OUTR0 Through OUTB3
TEST CIRCUITS
(1) X = R/G/B, n = 0-3.
(2) C
L
includes measurement probe and stray capacitance.
(1) C
L
includes measurement probe and stray capacitance.
Figure 4. Rise/Fall Time Test Circuit for OUTXn
Figure 5. Rise/Fall Time Test Circuit for
SDTO/SCKO
(1) X = R/G/B, n = 0-3.
Figure 6. Constant-Current Test Circuit for OUTXn
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