STMPE610 S-Touch®: advanced touchscreen controller with 6-bit port expander Features ■ 6 GPIOs ■ 1.8 - 3.
Contents STMPE610 Contents 1 STMPE610 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 3 I2C and SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 4 5 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interface selection . . . . . . . . . . . . . .
STMPE610 Contents 11 Touchscreen controller programming sequence . . . . . . . . . . . . . . . . . 40 12 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.0.1 13 Power-up reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . .
STMPE610 functional overview 1 STMPE610 STMPE610 functional overview The STMPE610 consists of the following blocks: ● I2C and SPI interface ● Analog-to-digital converver (ADC) ● Touchscreen controller (TSC) ● Driver and switch control unit ● GPIO controller Figure 1. STMPE610 functional block diagram '0)/ !$# ). -/$% 2EF 2EF '0)/ CONTROLLER 3WITCHES AND DRIVERS 2# OSCILLATOR !$# 43# ).4 $ATA IN ! $ATA OUT ) # 30) INTERFACE 3#,+ #,+ 3$!4 #3 62%& '.
STMPE610 2 Pin configuration and functions Pin configuration and functions Figure 2. STMPE610 pin configuration (top through view) 12 11 10 9 13 8 14 7 STMPE610 15 6 16 5 1 Table 2. 2 3 4 Pin assignments Pin Name Function 1 Y- 2 INT 3 A0/Data Out 4 SCLK I2C/SPI clock (VCC domain) 5 SDAT I2C data/SPI CS (VCC domain) 6 VCC 7 Data in 8 NC Y-/GPIO-7 Interrupt output (VCC domain, open drain) I2C address in Reset, Data out in SPI mode (VCC domain) 1.8 − 3.
Pin configuration and functions 2.1 STMPE610 Pin functions The STMPE610 is designed to provide maximum features and flexibility in a very small pincount package. Most of the pins are multi-functional. The following table shows how to select the pin’s function. Table 3.
STMPE610 I2C and SPI interface 3 I2C and SPI interface 3.1 Interface selection The STMPE610 interfaces with the host CPU via a I2C or SPI interface. The pin IN_1 allows the selection of interface protocol at reset state. Figure 3. STMPE610 interface DIN SPI I/F module DOUT CLK CS MUX unit I2C I/F module Table 5.
I2C interface 4 STMPE610 I2C interface The addressing scheme of STMPE610 is designed to allow up to 2 devices to be connected to the same I2C bus. Figure 4. STMPE610 I2C interface GND VCC SCLK SCLK SDAT SDAT STMPE610 ADDR0 AM00753V Table 6. I2C address ADDR0 Address 0 0 x 82 1 0 x 88 For the bus master to communicate to the slave device, the bus master must initiate a Start condition and be followed by the slave device address.
STMPE610 I2C interface Table 7. I2C timing Symbol Min Typ Max Unit 0 − 400 kHz fSCL SCL clock frequency tLOW Clock low period 1.
I2C interface STMPE610 the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it does not acknowledge the receipt of the data. 4.2 Data input The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low. Table 8.
STMPE610 I2C interface Stop Data Read + 2 No Ack Data Read + 1 Ack Stop No Ack Data Read Ack Ack R/W=1 Ack R/W=1 Data to Write + 2 Ack Stop Data to Write + 1 Ack Data to Write Ack Data to be written Data Read Ack Stop Ack Restart Ack Restart Reg Address Device Address Ack Reg Address Device Address Ack Ack R/W=0 Ack R/W=0 R/W=0 Device Address Reg Address Ack Device Address Reg Address Ack More than one byte Read Device Address R/W=0 One byte Write Start More tha
I2C interface 4.4 STMPE610 Write operations A write is first performed to load the register address into the Address Counter without sending a Stop condition. After the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the Address Counter). The slave device again acknowledges and the bus master terminates the transfer with a Stop condition.
STMPE610 5 SPI interface SPI interface The SPI interface in STMPE610 uses a 4-wire communication connection (DATA IN, DATA OUT, CLK, CS). In the diagram, “Data in” is referred to as MOSI (master out slave in) and “DATA out” is referred to as MISO (master in slave out). 5.1 SPI protocol definition The SPI (serial peripheral interface) follows a byte sized transfer protocol. All transfers begin with an assertion of CS_n signal (falling edge).
SPI interface 5.1.2 STMPE610 Register write The following steps need to be followed for register write through SPI. 5.1.3 1. Assert CS_n by driving a '0' on this pin. 2. Drive a '0' on the first SCL launch clock on MOSI to select a write operation. 3. The next 7 bits on MOSI denote the 7-bit register address (MSB first). 4. The next byte on the MOSI denotes data to be written. 5. The following transmissions on MOSI are considered byte-sized data.
STMPE610 SPI interface Table 10. SPI timing specification (continued) Timing Symbol Description Unit Min Typ Max tLDI Launch clock to MOSI data valid − − 20 ns tLDO Launch clock to MISO data valid − − 330 µs tDI Data on MOSI valid 1 − − µs tCCS Last clock edge to CS_n high 1 − − µs tCSH CS_n high period 2 − − µs tCSCL CS_n high to first clock edge 300 − − ns tCSZ CS_n high to tri-state on MISO 1 − − µs Figure 7.
STMPE610 registers 6 STMPE610 STMPE610 registers This section lists and describes the registers of the STMPE610 device, starting with a register map and then provides detailed descriptions of register types. Table 11.
STMPE610 STMPE610 registers Table 11.
System and identification registers 7 STMPE610 System and identification registers Table 12.
STMPE610 System and identification registers SYS_CTRL2 Clock control 7 6 5 4 3 2 1 0 - - - - RESERVED GPIO_OFF TSC_OFF ADC_OFF Address: 0x04 Type: R/W Reset: 0x0F Description: This register enables to switch off the clock supply [7:3] RESERVED [2] GPIO_OFF: Switch off the clock supply to the GPIO 1: Switches off the clock supply to the GPIO [1] TSC_OFF: Switch off the clock supplyto the touchscreen controller 1: Switches off the clock supply to the touchscreen controller [0] ADC_O
Interrupt system 8 STMPE610 Interrupt system The STMPE610 uses a 2-tier interrupt structure. The ADC interrupts and GPIO interrupts are ganged as a single bit in the “interrupt status register”. The interrupts from the touchscreen controller can be seen directly in the interrupt status register. Figure 8.
STMPE610 Interrupt system INT_CTRL 7 Interrupt control register 6 5 4 3 RESERVED 2 1 0 INT_POLARITY INT_TYPE GLOBAL_INT Address: 0x09 Type: R/W Reset: 0x00 Description: The interrupt control register is used to enable the interruption from a system-related interrupt source to the host.
Interrupt system STMPE610 INT_STA Interrupt status register 7 6 5 4 3 2 1 0 GPIO ADC RESERVED FIFO_EMPTY FIFO_FULL FIFO_OFLOW FIFO_TH TOUCH_DET Address: 0x0B Type: R Reset: 0x10 Description: The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless of whether the INT_EN bits are enabled, the INT_STA bits are still updated. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
STMPE610 Interrupt system GPIO interrupt enable register GPIO_INT_EN 7 6 5 4 3 2 1 0 IEG[x] Address: 0x0C Type: R/W Reset: 0x10 Description: The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless of whether the IER bits are enabled, the ISR bits are still updated. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
Analog-to-digital converter 9 STMPE610 Analog-to-digital converter An 8-input,12-bit analog-to-digital converter (ADC) is integrated in the STMPE610. The ADC can be used as a generic analog-to-digital converter, or as a touchscreen controller capable of controlling a 4-wire resistive touchscreen. AddINT_EN Table 13.
STMPE610 Analog-to-digital converter ADC_CTRL1 ADC control 1 7 RESERVED 6 5 4 SAMPLE_TIME2 SAMPLE_TIME1 SAMPLE_TIME0 Address: 0x20 Type: R/W Reset: 0x9C Description: ADC control register 3 2 1 0 MOD_12B RESERVED REF_SEL RESERVED [7] RESERVED [6:4] SAMPLE_TIMEn: ADC conversion time in number of clock 000: 36 001: 44 010: 56 011: 64 100: 80 101: 96 110: 124 111: Not valid [3] MOD_12B: Selects 10 or 12-bit ADC operation 1: 12 bit ADC 0: 10 bit ADC [2] RESERVED [1] REF_SEL: Selects betw
Analog-to-digital converter STMPE610 [1:0] ADC_FREQ: Selects the clock speed of ADC 00: 1.625 MHz typ. 01: 3.25 MHz typ. 10: 6.5 MHz typ. 11: 6.5 MHz typ. ADC channel data capture ADC_CAPT 7 6 5 4 3 2 1 0 CH[7:0] Address: 0x22 Type: R/W Reset: 0xFF Description: To initiate ADC data acquisition [7:0] CH[7:0]: ADC channel data capture Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect. Reads '1' if conversion is completed.
STMPE610 Analog-to-digital converter Table 14. ADC conversion time Sample time setting Conversion time 6.5 MHz 3.25 MHz 1.625 MHz in ADC clock (154 ns) (308 ns) (615 ns) 000 36 5.5 µs (180 kHz) 11 µs (90 kHz) 22 µs (45 kHz) 001 44 6.8 µs (147 kHz) 13.6 µs (74 kHz) 27 µs (36 kHz) 010 56 8.6 µs (116 kHz) 17.2 µs (58 kHz) 34.4 µs (29 kHz) 011 64 9.9 µs (101 kHz) 19.8 µs (51 kHz) 39.6 µs (25 kHz) 100 80 12.3 µs (81.5 kHz) 24.6 µs (41 kHz) 49.2 µs (20 kHz) 101 96 14.
Touchscreen controller 10 STMPE610 Touchscreen controller The STMPE610 is integrated with a hard-wired touchscreen controller for 4-wire resistive type touchscreen. The touchscreen controller is able to operate completely autonomously, and will interrupt the connected CPU only when a pre-defined event occurs. Figure 9. Touchscreen controller block diagram Movement & window tracking 10/12 bit ADC s FIFO FIFO & interrupt control 10.
STMPE610 Touchscreen controller Window tracking The -WDW_X and WDW_Y registers allow to pre-set a sub-window in the touchscreen such that any touch position that is outside the sub-window will be discarded. Figure 10. Window tracking Top right coordinates Active window Bottom left coordinates FIFO FIFO has a depth of 128 sectors. This is enough for 128 sets of touch data at maximum resolution (2 x 12 bits). FIFO can be programmed to generate an interrupt when it is filled to a pre-determined level.
Touchscreen controller STMPE610 Sampling time calculation The equation for a complete sampling cycle is described below. Touch Detect Delay Sampling Z Settling Time Sampling Y Settling Time Sampling X Settling Time Touch Detect Delay Figure 12.
STMPE610 Touchscreen controller Table 15.
Touchscreen controller STMPE610 TSC_CFG 7 Touchscreen controller configuration register 6 5 AVE_CTRL_1 AVE_CTRL_0 4 3 TOUCH_DET TOUCH_DET TOUCH_DET _DELAY_2 _DELAY_1 _DELAY_0 Address: 0x41 Type: R/W 2 1 0 SETTLING_2 SETTLING_1 SETTLING_0 Buffer: Reset: Description: Touchscreen controller configuration register.
STMPE610 10.2 Touchscreen controller Touch detect delay Touch Detect Delay is an additional method used to compensate for the time it takes for the panel voltage to be pulled high during a non-touch condition. For example, the way it works to detect a touch: X+ is pulled high and Y+ is driven low. After Touch Detect Delay is expired the level of X+ is read. If no touch, X+ is high. If there is a touch, X+ is low.
Touchscreen controller STMPE610 WDW_TR_X Window setup for top right X 7 6 5 4 3 2 1 0 TR_X [11:0] Address: 0x42 Type: R/W Reset: 0x0FFF Description: Window setup for top right X coordinates [11:0] TR_X: bit 11:0 of top right X coordinates WDW_TR_Y Window setup for top right Y 7 6 5 4 3 2 1 0 TR_Y [11:0] Address: 0x44 Type: R/W Reset: 0x0FFF Description: Window setup for top right Y coordinates [11:0] TR_X: bit 11:0 of top right Y coordinates WDW_BL_X Window setup f
STMPE610 Touchscreen controller FIFO_TH FIFO threshold 7 6 5 4 3 2 1 0 FIFO_TH Address: 0x4A Type: R/W Reset: 0x00 Description: Triggers an interrupt upon reaching or exceeding the threshold value. This field must not be set as zero. [7:0] FIFO_TH: Touchscreen controller FIFO threshold FIFO_CTRL_STA FIFO threshold 7 6 5 4 FIFO_OFLOW FIFO_FULL FIFO_EMPTY FIFO_TH_TRIG Address: 0x4B Type: R/W Reset: 0x20 Description: 3 2 RESERVED 1 0 FIFO_RESET Current status of FIFO..
Touchscreen controller STMPE610 FIFO_SIZE FIFO size 7 6 5 4 3 RESERVED 2 1 0 FIFO_SIZE Address: 0x4C Type: R Reset: 0x00 Description: Current number of samples available [7:0] FIFO_SIZE: Number of samples available TSC_DATA_X 11 10 TSC_DATA_X 9 8 7 6 5 4 3 2 1 0 DATAY[11:0] Address: 0x4D Type: R Reset: 0x0000 Description: Bit 11:0 of Y dataTSC_DATA_Y [11:0] DATAY[11:0]: Bit 11:0 of Y data TSC_DATA_Y 11 10 9 8 7 6 5 4 3 2 1 0 DATAY[11:0] Address: 0x4F
STMPE610 Touchscreen controller TSC_DATA Touchscreen controller DATA 7 6 5 4 3 2 1 0 DATA Address: 0x57 (auto-increment), 0xD7 (non-auto-increment) Type: R Reset: 0x00 Description: Data port for TSC data access [11:0] DATA: data bytes from TSC FIFO The data format from the TSC_DATA register depends on the setting of "OpMode" field in TSC_CTRL register. The samples acquired are accessed in "packed samples".
Touchscreen controller STMPE610 TSC_FRACTION_Z 7 6 Touchscreen controller FRACTION_Z 5 4 3 2 RESERVED 1 0 FRACTION_Z Address: 0x56 Type: R Reset: 0x00 Description: This register allows to select the range and accuracy of the pressure measurement [7:3] RESERVED [2:0] FRACTION_Z: 000: Fractional part is 0, whole part is 8 001: Fractional part is 1, whole part is 7 010: Fractional part is 2, whole part is 6 011: Fractional part is 3, whole part is 5 100: Fractional part is 4, whole part is 4
STMPE610 Touchscreen controller TSC_SHIELD 7 Touchscreen controller shield 6 5 RESERVED 4 3 2 1 0 X+ X- Y+ Y- Address: 0x59 Type: R Reset: 0x00 Description: Writing each bit would ground the corresponding touchscreen wire [7:4] RESERVED [3:0] SHIELD[3:0]: Write 1 to GND X+, X-, Y+, Y- lines Doc ID 15432 Rev 4 39/56
Touchscreen controller programming sequence 11 STMPE610 Touchscreen controller programming sequence The following are the steps to configure the touchscreen controller (TSC): a) Disable the clock gating for the touchscreen controller and ADC in the SYS_CFG2 register. b) Configure the touchscreen operating mode and the window tracking index. c) A touch detection status may also be enabled through enabling the corresponding interrupt flag.
STMPE610 Touchscreen controller programming sequence Z value. With the Z value obtained from the register, the user simply needs to multiply the Z value with the touchscreen panel resistance to obtain the touch resistance. o) The TSC_DATA register allows facilitation of another reading format with minimum I2C transaction overhead by using the non autoincrement mode (or equivalent mode in SPI).
GPIO controller 12 STMPE610 GPIO controller A total of 6 GPIOs are available in the STMPE610 port expander device. Most of the GPIOs share physical pins with some alternate functions. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to minimize power consumption. A group of registers are used to control the exact function of each of the 6 GPIOs.
STMPE610 GPIO controller GPIO_CLR_PIN Clear pin state register Address: 0x11 Type: R/W Reset: 0x00 Description: GPIO clear pin state register. Writing ‘1’ to this bit causes the corresponding GPIO to go to 0 state. Writing ‘0’ has no effect. GPIO_MP_STA GPIO monitor pin state register Address: 0x12 Type: R/W Reset: 0x00 Description: GPIO monitor pin state. Reading this bit yields the current state of the bit. Writing has no effect.
GPIO controller STMPE610 GPIO_RE Rising edge register Address: 0x15 Type: R/W Reset: 0x00 Description: GPIO rising edge detection enable register. Setting this bit to ‘1’ would enable the detection of the rising edge transition. The detection would be reflected in the GPIO edge detect status register. GPIO_FE Falling edge detection enable register Address: 0x16 Type: R/W Reset: 0x00 Description: Setting this bit to ‘1’ would enable the detection of the falling edge transition.
STMPE610 13 Maximum rating Maximum rating Stressing the device above the ratings listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 18.
Maximum rating Table 19. STMPE610 Power consumption (continued) Value Symbol IIOhibernate 46/56 Parameter I/O supply current Test condition Unit Min Typ Max Hibernate state, no I2C/SPI activity VIO = 1.8 − 3.3 V − 0.5 1 µA Hibernate state, no I2C/SPI activity VIO = 3.3 V − 1.0 3.
STMPE610 14 Electrical specifications Electrical specifications Table 20. DC electrical characteristics (-40 ° C to 85 ° C, all GPIOs comply to JEDEC standard JESD-8-7) Value Symbol Parameter Test condition Unit Min Typ Max VIL Input voltage low state VIO = 1.8 − 3.3 V -0.3 V − 0.20 VIO V VIH Input voltage high state VIO = 1.8 − 3.3 V 0.80 VIO − VIO + 0.3 V V VOL Output voltage low state VIO = 1.8 V, IOL = 4 mA Output voltage high VIO = 3.3 V, state IOL = 8 mA -0.3 V − 0.
Electrical specifications Table 22. STMPE610 ADC specification (-40 ° C to 85 ° C) Value Parameter Test condition Unit Min Typ Max Full-scale input span 0 − Vref V Absolute input range − − VCC +0.2 V Input capacitance − 25 − pF Leakage current − 0.
STMPE610 15 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. Package outline for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch 7185330_F 1. Drawing not to scale.
Package mechanical data Table 25. STMPE610 Package mechanical data for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch Millimeters Symbol Min Typ Max A 0.80 0.90 1.00 A1 − 0.02 0.05 A3 − 0.20 − b 0.18 0.25 0.30 D − 3.00 − D2 1.55 1.70 1.80 E − 3.00 − E2 1.55 1.70 1.80 e − 0.50 − K − 0.20 − L 0.30 0.40 0.50 r 0.09 − − Figure 14. Recommended footprint for QFN16 (3 x 3 x 1 mm) - 0.
STMPE610 Package mechanical data Table 26. Footprint dimensions Millimeters Symbol Min Typ Max A − 3.8 − B − 3.8 − C − 0.5 − D − 0.3 − E − 0.8 − F − 1.5 − G − 0.
Package mechanical data STMPE610 Figure 15. Carrier tape for QFN16 (3 x 3 x 1 mm) - 0.
STMPE610 Package mechanical data Figure 16. Reel information for QFN16 (3 x 3 x 1 mm) - 0.
Package mechanical data STMPE610 Figure 17.
STMPE610 16 Revision history Revision history Table 27. Document revision history Date Revision Changes 07-Apr-2009 1 Initial release. 23-Sep-2009 2 Removed “Temperature sensor” from Section 1, Figure 1 and Figure 8. Updated: In the SYS_CTRL2 register, the 3rd bit is reserved. 12-Mar-2010 3 Updated: Title of the document and ESD value in Table 18. 09-Sep-2011 4 Added new section: Section 10.
STMPE610 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.