Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 116 of 233
8.2.24. Memory Read (2Eh)
2Eh RAMRD (Memory Read)
D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 0 1 1 1 0 2Eh
1
st
Parameter 1 1 ↑ XX X X X X X X X X X
2
nd
Parameter 1 1 ↑ D1 [17:0] XX
: 1 1 ↑ Dx [17:0] XX
(N+1)
th
Parameter
1 1 ↑ Dn [17:0] XX
Description
This command transfers image data from ILI9341’s frame memory to the host processor starting at the pixel location
specified by preceding set_column_address and set_page_address commands.
If Memory Access control B5 = 0:
The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels are read from
frame memory at (SC, SP). The column register is then incremented and pixels read from the frame memory until the
column register equals the End Column (EC) value. The column register is then reset to SC and the page register is
incremented. Pixels are read from the frame memory until the page register equals the End Page (EP) value or the host
processor sends another command.
If Memory Access Control B5 = 1:
The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels are read from
frame memory at (SC, SP). The page register is then incremented and pixels read from the frame memory until the page
register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented.
Pixels are read from the frame memory until the column register equals the End Column (EC) value or the host processor
sends another command.
Restriction There is no restriction on length of parameters.
Register
Availability
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Normal Mode On, Idle Mode On, Sleep Out Yes
Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Default
Status Default Value
Power On Sequence Contents of memory is set randomly
SW Reset Contents of memory is set randomly
HW Reset Contents of memory is set randomly