Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 127 of 233
8.2.29. Memory Access Control (36h)
36h MADCTL (Memory Access Control)
D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 0 0 1 1 0 1 1 0 36h
Parameter 1 1 ↑ XX MY MX MV ML BGR MH 0 0 00
Description
This command defines read/write scanning direction of frame memory.
This command makes no change on the other driver status.
Bit Name Description
MY Row Address Order
MX Column Address Order
MV Row / Column Exchange
These 3 bits control MCU to memory write/read direction.
ML Vertical Refresh Order LCD vertical refresh direction control.
BGR RGB-BGR Order
Color selector switch control
(0=RGB color filter panel, 1=BGR color filter panel)
MH Horizontal Refresh ORDER LCD horizontal refreshing direction control.
Note: When BGR bit is changed, the new setting is active immediately without update the content in Frame Memory again.
X = Don’t care.
MV(Vertical refresh order bit)=" 1"MV(Vertical refresh order bit)="0"
overwrite
memory displaymemory display
Top-Left (0,0)Top-Left (0,0)
memory display
Send last (320)
Send 3rd (3)
Send 2nd (2)
Send 1st (1)
Top-Left (0,0)Top-Left (0,0)
memory display
Send 1st (1)
Send 3rd (3)
Send 2nd (2 )
Send last (320)
(example)
(example)
ML(Vertical refresh order bit)="1"ML(Vertical refresh order bit)="0"
R RG B G B
Driver IC
SIG1 SIG2 SIG240
R G B
LCD Panel
SIG1 SIG2 SIG240
R G B
R G B
R G B
R G B
R G B
R RG B G B
Driver IC
SIG1 SIG2 SIG240
RG B
LCD Panel
SIG1 SIG2 SIG240
RGB
R GB
RGB
RB G
RGB
BGR(RGB-BGR Order control bit)="0" BGR(RGB-BGR Order control bit )="1"