Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
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Page 154 of 233
8.3. Description of Level 2 Command
8.3.1. RGB Interface Signal Control (B0h)
B0h IFMODE (Interface Mode Control)
D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ XX 1 0 1 1 0 0 0 0 B0h
Parameter 1 1 ↑ XX ByPass_MODE
RCM
[1]
RCM
[0]
0 VSPL HSPL DPL EPL 40
Description
Sets the operation status of the display interface. The setting becomes effective as soon as the command is received.
EPL : DE polarity (“0”= High enable for RGB interface, “1”= Low enable for RGB interface)
DPL : DOTCLK polarity set (“0”= data fetched at the rising time, “1”= data fetched at the falling time)
HSPL : HSYNC polarity (“0”= Low level sync clock, “1”= High level sync clock)
VSPL : VSYNC polarity (“0”= Low level sync clock, “1”= High level sync clock)
RCM [1:0]: RGB interface selection (refer to the RGB interface section).
ByPass_MODE : Select display data path whether Memory or Direct to Shift register when RGB Interface is used.
ByPass_MODE Display Data Path
0
Direct to Shift Register ( default )
1 Memory
Restriction EXTC should be high to enable this command
Register
Availability
Status Availability
Normal Mode ON, Idle Mode OFF, Sleep OUT Yes
Normal Mode ON, Idle Mode ON, Sleep OUT Yes
Partial Mode ON, Idle Mode OFF, Sleep OUT Yes
Partial Mode ON, Idle Mode ON, Sleep OUT Yes
Sleep IN Yes
Default
Default Value
Status
ByPass_MODE RCM [1:0] VSPL HSPL DPL EPL
Power ON Sequence 1’b0 2’b10 1’b0 1’b0 1’b0 1’b1
SW Reset 1’b0 2’b10 1’b0 1’b0 1’b0 1’b1
HW Reset 1’b0 2’b10 1’b0 1’b0 1’b0 1’b1