Data Sheet

STMPE610 I2C interface
Doc ID 15432 Rev 4 9/56
4.1 I
2
C features
The features that are supported by the I
2
C interface are listed below:
● I
2
C slave device
● Operates at 1.8 V
● Compliant to Philips I
2
C specification version 2.1
● Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I
2
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
Table 7. I
2
C timing
Symbol Parameter Min Typ Max Unit
f
SCL
SCL clock frequency 0
−
400 kHz
t
LOW
Clock low period 1.3
−−
µs
t
HIGH
Clock high period 600
−−
ns
t
F
SDA and SCL fall time
−−
300 ns
t
HD:STA
START condition hold time (after this
period the first clock is generated)
600
−−
ns
t
SU:STA
START condition setup time (only relevant
for a repeated start period)
600
−−
ns
t
SU:DAT
Data setup time 100
−−
ns
t
HD:DAT
Data hold time 0
−−
µs
t
SU:STO
STOP condition setup time 600
−−
ns
t
BUF
Time the bus must be free before a new
transmission can start
1.3
−−
µs