Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 35 of 233
Host processor drives the CSX pin to low and starts by setting the D/CX bit on SDA. The bit is read by ILI93401
on the first rising edge of SCL signal. On the next falling edge of SCL, the MSB data bit (D7) is set on SDA by
the host. On the next falling edge of SCL, the next bit (D6) is set on SDA. If the optional D/CX signal is used, a
byte is eight read cycle width. The 3/4-line serial interface writes sequence described in the figure as below.
S TB P
D6D7 D5 D4 D2D3 D1 D0
0
D6D7 D5 D4 D2D3 D1 D0D/C
TB
CSX
SDA
SCL
Command Data / Command / Parameter
The CSX can be high level between the data and
next command.The SDA and SCL are invalid during
CSX is high level
Host
(MCU to Driver)
3-line Serial Interface Protocol
S T B
P
D 6D 7 D 5 D 4 D 2D 3 D 6D 7 D 5 D 4 D 2D 3 D 1 D 0
T B
C S X
D /C X
S C L
C o m m a n d
C S X c a n b e "H " b e tw e e n c o m m a n d /
c o m m a n d a n d p a r a m e te r / c o m m a n d . S C L a n d
S D A d u rin g C S X = "H " is in v a lid .
S D A
T B
D /C
0
D 1 D 0
4 -lin e S e ria l In te rfa c e P ro to c o l
D a ta / C o m m a n d / P a ra m e te r