Data Sheet

a-Si TFT LCD Single Chip Driver

240RGBx320 Resolution and 262K color

ILI9341

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 47 of 233

frequency about 70Hz.

Notes:

1. Vertical period (one frame) shall be equal to the sum of Vsync + VBP + VAdr + VFP.

2. Horizontal period (one line) shall be equal to the sum of Hsync + HBP + HAdr + HFP.

3. Control signals PCLK and Hsync shall be transmitted as specified at all times while valid pixels are transferred

between the host processor and the display module.

Also make sure that

(Number of PCLK per 1 line) ≥ (Number of RTN clock) x Division ratio (DIV) x PCDIV

Setting Example for Display Control Clock in RGB Interface Operation

DOTCLK.

PCDIV [5:0]: Number of DOTCLK during internal clock PCLKD’s high / low period. In units of 1 clock.

PCDIV specifying DOTCLK’s division ratio, are determined so that difference between PCLKD’s frequency

and internal oscillation clock 615KHz is the smallest. Set PCDIV follow the restriction

(Number of PCLK in 1H) ≥ (Number of RTN clock) x Division ratio (DIV) x PCDIV.

Setting Example: To set frame frequency to 70Hz:

Internal Clock

Internal Oscillation Clock: 615KHz

DIV[1:0] = 2’b0 (x 1/1)

RTN[4:0] = 5’h1b (27 clocks)

FP = 7'h2 (2 lines), BP = 7'h2 (2 lines), NL = 6’h27 (320 lines)

Frame Rate 



 70.30Hz

DOTCLK

HSYNC = 10 CLK

HBP = 20 CLK

HFP=10 CLK

70Hz x (2 + 320 + 2) lines x (10 + 20 + 240 + 10) clocks = 6.35MHz

DOTCLK frequency = 6.35MHz

6.35 MHz / 615KHz = 10.32  Set PCDIV so that PCLK is divided by 10.

external fosc = 6.35 MHz / 10 = 635KHz

PCDIV = [ 6.35MHz / 635KHz) / 2 ] - 1 = 4

PCDIV[5:0] = 6’h04 (10 DOTCLK)