Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 50 of 233
The timing chart of 6-bit RGB interface mode is shown as below:
HSYNC
VSYNC
DOTCLK
ENABLE
D[5:0]
Back porch
VLW>=1H
1 frame
Front porch
Valid data
HLW>=2DOTCLKs
1H
DTST>=HLW
HSYNC
DOTCLK
ENABLE
D[5:0]
VLW : VSYNC Low Width
HLW : HSYNC Low Width
DTST : Data Transfer Startup Time
R G B R G B B R G B
DOTCLK
PCLKD
PCDIVH[3:0] PCDIVL[3:0]
Note 1: The DE signal is not needed when RGB interface SYNC mode is selected.
Note 2: VSPL=’0’, HSPL=’0’, DPL=’0’ and EPL=’0’ of “Interface Mode Control (B0h)” command.
Note 3: In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with
DOTCLK.