Data Sheet

a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9341
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 53 of 233
The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system
interface, which are calculated from the following formula.
Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (VFP) + BackPorch
(VBP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
Minimum RAM write speed [Hz]
(1/fosc)line perClocks margins]es(NL)DisplayLin(VBP)[BackPorch
es(NL)DisplayLin240
××−+
×
Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling
edge of VSYNC until the start of RAM write operation must also be taken into account.
An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as
below.
[Example]
Display size: 240 RGB × 320 lines
Lines: 320 lines (NL = 100111)
Back porch: 2 lines (VBP = 0000010)
Front porch: 2 lines (VFP = 0000010)
Frame frequency: 70 Hz
Frequency fluctuation: 10%
Internal oscillator clock (fosc.) [Hz] = 70 x [320+ 2 + 2] x 27 clocks x (1.1/0.9) 748KHz