Datasheet

MPL3115A2
Sensors
16 Freescale Semiconductor, Inc.
The number of bytes per transfer is unlimited. If the master can't receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when
the master is ready for another byte and releases the clock line.
A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer is
always terminated by a STOP. A master may also issue a repeated START during a data transfer. Device expects repeated
STARTs to be used to randomly read from specific registers.
The standard 7-bit I
2
C slave address is 0x60 or 1100000. 8-bit read is 0xC1, 8-bit write is 0xC0.
Consult factory for alternate addresses. See the application note titled Sensor I
2
C Setup and FAQ (document AN4481).