Datasheet
MB85RS64V
DS501-00015-4v0-E 9
READ
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ
are input to SI. The 3-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keeps on reading with automatic address increment which is enabled by con-
tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant
address, it rolls over to the starting address, and reading cycle keeps on infinitely.
WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The 3-bit upper address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command. However,
if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with
automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle keeps on infinitely.
SO
SCK
SI
CS
0 0 00 X1 12 10
MSB
76543210
Data Out
MSB
High-Z
LSB
4 2 01
Invalid
131211109
8 2
5
24232221201918 313029282726
OP-CODE
0 0 1 11XX 35
16-bit Address
Invalid
LSB
2 0136 457
SO
SCK
SI
CS
0 0 00 X1 12 10
MSB
76543210
Data In
MSB
High-Z
LSB
4 2 01
131211109
8 2
5
24232221201918 313029282726
OP-CODE
0 0 0 11XX 35
16-bit Address
LSB
2 0136 457