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MAX98357A/MAX98357B

PCM Input Class D Audio Power Amplifiers

19-6779; Rev 7; 2/16

General Description

The MAX98357A/MAX98357B are digital pulse-code

modulation (PCM) input Class D power amplifiers that

provide Class AB audio performance with Class D effi-

ciency. These ICs offer five selectable gain settings

(3dB, 6dB, 9dB, 12dB, and 15dB) in I

S/left-justified

mode set by a single gain select input and a fixed 12dB

gain in TDM mode.

The digital audio interface is highly flexible with the

MAX98357A supporting I

S data and the MAX98357B sup-

porting left-justified data. Both ICs support 8 channel time

division multiplexed (TDM) data. The digital audio interface

accepts specified sample rates between 8kHz and 96kHz

for all supported data formats. The ICs can be configured

to produce a left channel, right channel, or (left/2 + right/2)

output from the stereo input data. The ICs operate using

16/24/32-bit data for I

S and left-justified modes as well as

16-bit or 32-bit data using TDM mode. The ICs eliminate

the need for the external MCLK signal that is typically used

for PCM communication. This reduces EMI and possible

board coupling issues in addition to reducing the size and

pin count of the ICs.

The ICs also feature a very high wideband jitter tolerance

(12ns typ) on BCLK and LRCLK to provide robust operation.

Active emissions-limiting, edge-rate limiting, and over-

shoot control circuitry greatly reduce EMI. A filterless

spread-spectrum modulation scheme eliminates the

need for output filtering found in traditional Class D

devices and reduces the component count of the solution.

The ICs are available in 9-pin WLP (1.345mm x 1.435mm

x 0.64mm) and 16-pin TQFN (3mm x 3mm x 0.75mm)

packages and are specified over the -40NC to +85NC

temperature range.

Applications

Notebook and Netbook Computers

Cellular Phones

Tablets

Features

S Single-Supply Operation (2.5V to 5.5V)

S 3.2W Output Power into 4I at 5V

S 2.4mA Quiescent Current

S 92% Efficiency (R

= 8I, P

OUT

= 1W)

S 25µV

RMS

Output Noise (A

= 15dB)

S Low 0.015% THD+N at 1kHz

S No MCLK Required

S Sample Rates of 8kHz to 96kHz

S Supports Left, Right, or (Left/2 + Right/2) Output

S Sophisticated Edge Rate Control Enables

Filterless Class D Outputs

S 77dB PSRR at 1kHz

S Low RF Susceptibility Rejects TDMA

Noise from GSM Radios

S Extensive Click-and-Pop Reduction Circuitry

S Robust Short-Circuit and Thermal Protection

S Available in Space-Saving Packages:

1.345mm x 1.435mm WLP (0.4mm Pitch)

and 3mm x 3mm TQFN

Ordering Information appears at end of data sheet.

Functional Diagram appears at end of data sheet.

Simplified Block Diagram

EVALUATION KIT AVAILABLE

DAC

CLASS D

OUTPUT

STAGE

DIGITAL

AUDIO

INTERFACE

PCM

INPUT

GAIN

CONTROL

SHUTDOWN

AND

CHANNEL

SELECT

MAX98357A

MAX98357B

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Summary of content (38 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers General Description Features The MAX98357A/MAX98357B are digital pulse-code modulation (PCM) input Class D power amplifiers that provide Class AB audio performance with Class D efficiency. These ICs offer five selectable gain settings (3dB, 6dB, 9dB, 12dB, and 15dB) in I2S/left-justified mode set by a single gain select input and a fixed 12dB gain in TDM mode. S Single-Supply Operation (2.5V to 5.
PAGE 2
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers LIST OF FIGURES Figure 1. I2S Audio Interface Timing Diagram (MAX98357A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98357B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TDM Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers ABSOLUTE MAXIMUM RATINGS VDD, LRCLK, BCLK, and DIN to GND.....................-0.3V to +6V All Other Pins to GND............................... -0.3V to (VDD + 0.3V) Continuous Current In/Out of VDD/GND/OUT_.................. Q1.6A Continuous Input Current (all other pins)......................... Q20mA Duration of OUT_ Short Circuit to GND or VDD…......Continuous Duration of OUTP Short to OUTN..............................
PAGE 5
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = VDD. BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS THD+N 10%, gain = 12dB Output Power (Note 3) POUT THD+N = 1%, gain = 12dB Total Harmonic Distortion + Noise THD+N MIN TYP ZSPK = 4I + 33FH 3.
PAGE 6
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD. BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AUDIO MODE FIR LOWPASS FILTER (30kHz < LRCLK < 50kHz) Passband Cutoff Stopband Cutoff fPLP Ripple limit cutoff 0.43 x fS -3dB cutoff 0.
PAGE 7
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD. BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.
PAGE 8
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers tBCLK tBCLKH BCLK (INPUT) VIH VIH VIL VIH VIL tBCLKL VIL tSYNCHOLD tSYNCSET VIH LRCLK (INPUT) VIL tSETUP tHOLD VIH DIN (INPUT) VIL RIGHT MSB LEFT MSB Figure 1. I2S Audio Interface Timing Diagram (MAX98357A) tBCLK tBCLKH BCLK (INPUT) VIH VIH VIL VIH VIL tBCLKL VIL tSYNCHOLD tSYNCSET VIH LRCLK (INPUT) VIL tSETUP tHOLD DIN (INPUT) LEFT MSB VIL VIH RIGHT MSB Figure 2.
PAGE 9
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) QUIESCENT CURRENT vs. SUPPLY VOLTAGE 4.0 toc01 SHUTDOWN CURRENT (µA) 2.5 2.0 1.5 1.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 toc03 f = 1kHz -60 -80 f = 1kHz 0 VDD = 3.
PAGE 10
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) TOTAL HARMONIC DISTORTION PLUS NOISE vs.
PAGE 11
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) OUTPUT POWER vs. SUPPLY VOLTAGE toc18 ZSPK = 8Ω + 68µH OUTPUT POWER (W) OUTPUT POWER (W) ZSPK = 4Ω + 33µH 2 THD+N = 10% 3.0 THD+N = 1% 1.5 1.0 0.5 2.5 THD+N = 1% 2.0 1.5 1.0 0.
PAGE 12
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) POWER-SUPPLY REJECTION RATIO vs.
PAGE 13
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.
PAGE 14
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) fBCLK = 3.072MHz fLRCLK = 48kHz ZSPK = 8Ω + 68μ H 0 -80 -80 -60 -80 -100 -120 -120 -140 -140 5000 10000 15000 FREQUENCY (Hz) INBAND OUTPUT SPECTRUM 0 20000 toc46 fBCLK = 5.
PAGE 15
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Pin Configurations TOP VIEW BUMP SIDE DOWN DIN GAIN_SLOT OUTN B1 B2 B3 BCLK GND LRCLK C1 C2 C3 OUTP A3 11 10 9 N.C. 13 LRCLK 14 MAX98357A MAX98357B GND 15 BCLK 16 WLP + 1 2 3 4 SD_MODE A2 OUTN A1 12 GND OUTP GND VDD GAIN_SLOT SD_MODE DIN + N.C. TOP VIEW MAX98357A MAX98357B 8 VDD 7 VDD 6 N.C. 5 N.C.
PAGE 16
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Detailed Description The MAX98357A/MAX98357B are digital PCM input Class D power amplifiers. The MAX98357A accepts standard I2S data through DIN, BCLK, and LRCLK while the MAX98357B accepts left-justified data through the same inputs. Both versions also accept 16-bit or 32-bit TDM data with up to eight slots. The digital audio interface eliminates the need for an external MCLK signal that is typically required for I2S data transmission.
PAGE 17
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers cally enter standby mode. In standby mode, the Class D speaker is turned off and the outputs go into a highimpedance state, ensuring that unwanted current is not transferred to the load during this condition. Standby mode has reduced power consumption from normal operation (340µA), but does not reach as low as full shutdown (0.6µA). Standby mode can be used to reduce power consumption when no GPIO us available to pull SD_MODE low.
PAGE 18
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers PROCESSOR VDDIO R VSD_MODE GPIO LEFT MODE MAX98357A MAX98357B B2 (1.4V typ) RIGHT MODE 100kI ±8% B1 (0.77V typ) LEFT/2 + RIGHT/2 MODE B0 (0.16V typ) Figure 4. SD_MODE Resistor Connected Using Open-Drain Driver PROCESSOR MAX98357A MAX98357B VDDIO GPIO R VSD_MODE LEFT MODE B2 (1.4V typ) RIGHT MODE 100kI ±8% B1 (0.77V typ) LEFT/2 + RIGHT/2 MODE B0 (0.16V typ) Figure 5.
PAGE 19
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers I2S and Left Justified Mode The MAX98357A follows standard I2S timing by allowing a delay of one BCLK cycle after the LRCLK transition before the beginning of a new data word (Figure 6 and Figure 7). The MAX98357B follows the left justified timing specification by aligning the LRCLK transitions with the beginning of a new data word (Figure 8 and Figure 9). LRCLK ONLY supports 8kHz, 16kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz frequencies.
PAGE 20
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers 16 BITS/CHANNEL SD_MODE = VDD LRCLK RIGHT LEFT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED 16 BITS/CHANNEL SD_MODE PULL UP THROUGH RSMALL (70K) LRCLK RIGHT LEFT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED 16 BITS/CHANNEL SD_MODE PULL UP THROUGH RLA
PAGE 21
Maxim Integrated DIN BCLK LRCLK LEFT RIGHT LEFT RIGHT IGNORED RIGHT LEFT AND RIGHT SUMMED D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 LEFT IGNORED D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D28 D27 D26 D25 D24 D2
PAGE 22
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers 16 BITS/CHANNEL, SD_MODE = VDD LRCLK LEFT RIGHT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED 16 BITS/CHANNEL, SD_MODE PULLUP THROUGH RSMALL (70k) LRCLK LEFT RIGHT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED 16 BITS/CHANNEL, SD_MODE PULLUP THROUGH RLARGE (300k)
PAGE 23
Maxim Integrated SDIN BCLK LRCLK DIN BCLK LRCLK DIN BCLK LRCLK LEFT LEFT LEFT D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 32 BITS/CHANNEL, SD_MODE PULLUP THROUGH RLARGE (300k) IGNORED D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 32 BITS/CHANNEL, SD_MODE PULLUP THROUGH RSMALL (70k) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 32 BITS/CHANNEL, SD_MODE =
PAGE 24
Maxim Integrated IGNORED IGNORED TDM 16-BIT DATA, 128-BIT FRAME, DATA IN CHANNELS 1-6 D1 D0 IGNORED D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IGNORED D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TDM 16-BIT DATA, 128-BIT FRAME SD_MODE TIED TO VDD THROUGH RLARGE, GAIN_SLOT TIED TO VDD, DATA IN CHANNEL 7 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TDM 16-BIT DATA, 128-BIT FRAME SD_MODE TIED TO VDD, GAIN_SLOT TIED TO GND, DATA IN CHANNEL 0 D15 D14 LD3 MAX98357A/MAX98357
PAGE 25
Maxim Integrated IGNORED D8 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 TDM 32-BIT DATA, 256-BIT FRAME SD_MODE TIED TO VDD THROUGH RLARGE, GAIN_SLOT TIED TO VDD, DATA IN CHANNEL 7 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 TDM 32-BIT DATA, 256-BIT FRAME SD_MODE TIED TO VDD, GAIN_SLOT TIED TO GND, DATA IN CHANNEL 0 D8 D7 D6 IGNORED D5 D4 D3 D2 D1 D0 D31 D30 D29 MAX98
PAGE 26
Maxim Integrated D8 D7 D6 D5 D4 D3 D2 D1 D0 IGNORED TDM 16-BIT DATA, 128-BIT FRAME DATA IN CHANNELS 1-6 D1 D0 D15 D14 D13 D12 D11 D10 D9 IGNORED D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 IGNORED D15 D14 D13 D12 D11 D10 D9 TDM 16-BIT DATA, 128-BIT FRAME SD_MODE TIED TO VDD THROUGH RLARGE, GAIN_SLOT TIED TO VDD, DATA IN CHANNEL 7 D15 D14 D13 D12 D11 D10 D9 TDM 16-BIT DATA, 128-BIT FRAME SD_MODE TIED TO VDD, GAIN_SLOT TIED TO GND, DATA IN CHANNEL 0 D7 D6 D5 D4 D3 D1 IGNORED D2 D0 D15 D
PAGE 27
Maxim Integrated IGNORED IGNORED D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D0 TDM 32-BIT DATA, 256-BIT FRAME SD_MODE TIED TO VDD THROUGH RLARGE, GAIN_SLOT TIED TO VDD, DATA IN CHANNEL 7 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D0 TDM 32-BIT DATA, 256-BIT FRAME SD_MODE TIED TO VDD, GAIN_SLOT TIED TO GND, DATA IN CHANNEL 0 D31 D30 D29 MAX9
PAGE 28
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Class D Speaker Amplifier The filterless Class D amplifier offers much higher efficiency than Class AB amplifiers. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance and quiescent current overhead.
PAGE 29
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Applications Information 2.5V TO 5.5V 10µF 0.1µF CODEC GPIO* BIT CLOCK FRAME CLOCK DATA OUT SD_MODE BCLK LRCLK DIN A1 GAIN_SLOT B2 VDD A2 A3 C1 C3 MAX98357A MAX98357B B3 B1 OUTP OUTN C2 GND *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH. THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW. Figure 15. Left-Channel PCM Operation with 6dB Gain 2.5V TO 5.5V 10µF 0.
PAGE 30
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers 2.5V TO 5.5V 10µF CODEC RSMALL (69.8kI)** GPIO* 0.1µF VDD GAIN_SLOT SD_MODE A1 C1 LRCLK FRAME CLOCK C3 DIN DATA OUT A2 A3 BCLK BIT CLOCK B2 MAX98357A MAX98357B B3 B1 OUTP OUTN C2 GND *RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH. **69.8kI ASSUMES VGPIO = 1.8V. THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW. Figure 17. Right-Channel PCM Operation with 6dB Gain 2.5V TO 5.
PAGE 31
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers 2.5V TO 5.5V 10µF 0.1µF VDD GAIN_SLOT SD_MODE BCLK LRCLK DIN A1 B2 A2 A3 C1 OUTP MAX98357A MAX98357B C3 B3 B1 OUTN C2 GND CODEC *RESPONDS TO CHANNEL 0 WHEN GPIO IS HIGH. THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW. GPIO* BIT CLOCK 2.5V TO 5.5V FRAME CLOCK 10µF DATA OUT RSMALL (69.8kI)** 0.
PAGE 32
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers 2.5V TO 5.5V 0.1µF VDD GAIN_SLOT SD_MODE BCLK LRCLK DIN A1 B2 A2 A3 C1 C3 10µF OUTP MAX98357A MAX98357B B3 B1 OUTN C2 GND *RESPONDS TO CHANNEL 0 WHEN GPIO IS HIGH. THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW. 2.5V TO 5.5V 0.1µF CODEC GPIO* BIT CLOCK VDD GAIN_SLOT SD_MODE BCLK LRCLK FRAME CLOCK DIN A1 B2 A2 A3 C1 C3 10µF OUTP MAX98357A MAX98357B B3 B1 OUTN C2 DATA OUT GND *RESPONDS TO CHANNEL 1 WHEN GPIO IS HIGH.
PAGE 33
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Functional Diagram 2.5V TO 5.5V 10µF 0.1µF VDD GAIN_SLOT A2 MAX98357A MAX98357B LRCLK C3 BCLK C1 DIN B1 SD_MODE A1 B2 DIGITAL AUDIO INTERFACE INTERPOLATOR DAC CLASS D OUTPUT STAGE A3 OUTP B3 OUTN C2 GND Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filter adds cost, size, and decreases efficiency and THD+N performance.
PAGE 34
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: Wafer-Level Packaging (WLP) and Its Applications. Figure 21 shows the dimensions of the WLP balls used on the ICs. 0.24mm 0.21mm Figure 21.
PAGE 35
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 36
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PAGE 37
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PAGE 38
MAX98357A/MAX98357B PCM Input Class D Audio Power Amplifiers Revision History REVISION NUMBER REVISION DATE 0 9/13 Initial release 1 11/13 Added two new TOCs, replaced TOC 29, updated Figures 1–3, and made various corrections 2 8/14 Added THD+N for TQFN package with typical spec 3 1/15 Updated spread-spectrum bandwidth spec 4 2/15 Added automotive-qualified part 34 5 6/15 Updated TOCs 30a and 30b 12 6 8/15 Corrected package outline for WLP package 36 7 2/16 Removed future product