Datasheet
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
OH
V
IH
V
T
V
IL
V
OL
GND
5 V
4.44 V
0.7V
CC
0.5V
CC
0.3V
CC
0.5 V
0 V
V
IH
V
IL
GND
V
OH
V
IH
V
T
V
IL
V
IL
V
OL
GND
5 V
2.4 V
2 V
1.5 V
0.8 V
0.4 V
0 V
V
OH
V
IH
V
T
V
OL
GND
3.3 V
2.4 V
2 V
1.5 V
0.8 V
0.4 V
0 V
2.5 V
2.0 V
1.7 V
0.7 V
0.4 V
0 V
V
OH
V
IH
V
IL
V
OL
GND
1.8 V
V
CC
-0.45 V
0.65V
CC
0.35V
CC
0.45 V
0 V
V
OH
V
IH
V
IL
V
OL
GND
1.2 V
0.65V
CC
0.35V
CC
0 V
V
CC
1.5 V
0.65V
CC
0.35V
CC
0 V
V
IH
V
IL
GND
5V CMOS
5V TTL
3.3V LVTTL
2.5V CMOS
1.8V CMOS
1.5V CMOS 1.2V CMOS
The Need For Voltage-Level Translation
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1 The Need For Voltage-Level Translation
The need for voltage level translation is becoming increasingly significant in today's electronic systems. As
the digital switching level standards have continued to progress toward lower voltage levels, system
incompatibilities have arisen. Figure 1 illustrates the trend toward lower system voltage levels and
demonstrates the incompatibilities that mixed voltage systems can face.
Figure 1. Digital Switching Levels
For two devices to interface reliably, the output driver voltages must be compatible with receiver input
thresholds. For this condition to be met in mixed voltage systems, a voltage translator is often required.
Texas Instruments offers several unique device architectures for addressing voltage translation needs.
The most familiar to system designers is probably a direction controlled buffer translator, such as the
SN74AVC8T245. These translators can help remedy many problems in system voltage compatibility but
do require DIR (direction) control pins. If the system environment does not provide a programmable GPIO
to control the direction pin, an auto-direction sensing translator architecture can provide an alternative
translation solution.
2 Auto-Direction Sensing Voltage Translator Architecture
If a processer GPIO input direction-control signal is not available or if one is not desired, an auto-direction
sensing voltage translator can provide a robust solution. As the name implies, this type of translator does
not require the use of a direction control signal, and each channel supports independent transmission or
reception of data. This eliminates the need for a processor GPIO to control a DIR input, resulting in
simplified software driver development as well as smaller device packaging due to reduced pin-count.
The TXB push-pull buffered type architecture does not require a DIR control signal to establish the
direction of data flow. This architecture is designed to exclusively be connected and interfaced with a
push-pull CMOS driver and is capable of driving a capacitive or high impedance loads in applications such
as Secure Digital (SD) or Serial Peripheral Interface (SPI). The TXB010x devices are not intended for use
in open-drain applications. For applications such as I
2
C where there is a need to connect and interface
with an open-drain driver, TI offers TXS-type (i.e., "S" for Switch-type) translators. Please refer to TI
application report, A Guide to Voltage Translation With TXS-Type Translators, literature number SCEA044
for more information on the TXS-type voltage translators.
Figure 2 shows the basic architecture of a single-bit (or channel) of the TXB010x device.
2
A Guide to Voltage Translation With TXB-Type Translators SCEA043–March 2010
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