Datasheet

TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
13
The LUMENOLOGY r Company
r
r
Copyright E 2009, TAOS Inc.
www.taosinc.com
Wr
8
Data Byte 1Slave AddressS
1
A A
811 1
Command Code
P
Data Byte N A
811
Byte Count = N A A
...
7
811
Data Byte 2 A
81
...
Figure 16. SMBus Block Write or I
2
C Write Protocols
NOTE: The I
2
C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Wr
7
Byte Count = NSlave AddressS
1
A A
811 1
Command Code
PData Byte N A
811
Slave Address A A
...
7
811
Data Byte 2 A
81
...
Data Byte 1 A
81
1
Sr
1
Rd
1
Figure 17. SMBus Block Read or I
2
C Read (Combined Format) Protocols
NOTE: The I
2
C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS RESISTER NAME REGISTER FUNCTION
−− COMMAND Specifies register address
0h CONTROL Control of basic functions
1h TIMING Integration time/gain control
2h THRESHLOWLOW Low byte of low interrupt threshold
3h THRESHLOWHIGH High byte of low interrupt threshold
4h THRESHHIGHLOW Low byte of high interrupt threshold
5h THRESHHIGHHIGH High byte of high interrupt threshold
6h INTERRUPT Interrupt control
7h −− Reserved
8h CRC Factory test — not a user register
9h −− Reserved
Ah ID Part number/ Rev ID
Bh −− Reserved
Ch DATA0LOW Low byte of ADC channel 0
Dh DATA0HIGH High byte of ADC channel 0
Eh DATA1LOW Low byte of ADC channel 1
Fh DATA1HIGH High byte of ADC channel 1
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.