Programmer’s Manual AIC-6915 Ethernet LAN Controller R Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130-00, Rev. A Print Spec Number: 497767-00, Rev.
Adaptec, Inc. 691 South Milpitas Boulevard Milpitas, CA 95035 © 1998, Adaptec, Inc. All rights reserved. Adaptec and the Adaptec logo are registered trademarks of Adaptec, Inc. Printed in Singapore STOCK NO: 512130-00, Rev. A SG 9/98 Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130-00, Rev. A Print Spec Number: 497767-00, Rev.
▼ ▼ ▼ ▼ ▼ AIC-6915 Ethernet LAN Controller Programmer’s Manual R Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev.
Copyright © 1998 Adaptec, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of Adaptec, Inc., 691 South Milpitas Blvd., Milpitas, CA 95035. Trademarks Adaptec and the Adaptec logo are trademarks of Adaptec, Inc. which may be registered in some jurisdictions. All other trademarks are owned by their respective owners.
▼ ▼ ▼ ▼ 1 Contents Introduction Features 1-2 General 1-2 Ethernet 1-2 DMA 1-2 Internal Buffer Management 1-3 32/64-bit PCI 1-3 Block Diagram 1-5 Modules 1-6 2 Receive Architecture Features 2-1 Host Data Structures 2-2 Producer and Consumer Indices 2-2 Receive DMA Descriptor Queues 2-2 Normal Mode 2-3 Polling Mode 2-3 32-bit Addressing Mode 2-4 64-bit Addressing Mode 2-4 Completion/Status Descriptor Queue 2-4 Accepting frames 2-5 Completion Descriptor 2-5 3 Transmit Architecture Features 3-1 Transmit
AIC-6915 Ethernet LAN Controller Programmer’s Manual 4 PCI Module Architecture Features 4-1 PCI Block Diagram 4-3 PCI Master Module 4-4 64-bit PCI Bus Master 4-5 Arbitration 4-6 PCI Target Module 4-6 Power Management 4-8 CardBus 4-9 Retry Function 4-9 Response to PCI Commands 4-9 Configuration Address Space 4-11 I/O Address Space (Direct Access) 4-11 I/O Address Space (Indirect Access) 4-11 Expansion ROM Address Space 4-12 Memory Address Space 4-12 Parity 4-12 SERR_ 4-12 PERR_ 4-13 The Command And Byte En
Contents 7 Register Descriptions Overview 7-1 AIC-6915 Address Space 7-2 AIC-6915 PCI Address Map 7-2 Terminology 7-4 AIC-6915 Internal Registers 7-4 PCI Registers 7-5 PCI Configuration Header Registers 7-5 PCI Functional Registers Definition 7-17 Ethernet Registers 7-27 General Ethernet Functional Registers 7-27 Transmit Registers 7-37 Completion Queue Registers 7-43 Receive Registers 7-48 PCI Diagnostic Registers 7-59 PCI CardBus Registers 7-66 Additional Ethernet Registers 7-69 Ethernet Physical Device
AIC-6915 Ethernet LAN Controller Programmer’s Manual Transmit Buffer Descriptor Types 8-18 Two Transmit Queues 8-20 Transmit Producer-Consumer Model 8-20 Transmit Initialization 8-21 Transmit Handling 8-25 Transmit Completion Interrupt Handling 8-27 AIC-6915 DDK Features 8-29 DDK Development Environment 8-30 vi
▼ ▼ ▼ ▼ Figures Figure 1-1 AIC-6915 Block Diagram 1-5 2-1 The AIC-6915 Receive Data Structures 2-2 3-1 4-1 4-2 Transmit Host Communication Data Structure 3-4 PCI Block Diagram 4-3 64-bit PCI Reset Timing 4-5 5-1 Data Processing Unit 5-5 7-1 AIC-6915 PCI Address Map 7-3 Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev.
Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev.
▼ ▼ ▼ ▼ Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 Receive Buffer Descriptor (One-size, 32-bit Addressing) 2-4 Receive Buffer Descriptor (One-size Buffer, 64-bit Addressing) 2-4 Short (Type 0) Completion Entry 2-6 Basic (Type 1) Completion Descriptor 2-6 Checksum (Type 2) Completion Descriptor 2-6 Full (Type 3) Completion Descriptor 2-6 Receive Completion Descriptor (Word 0) 2-7 Receive Completion Descriptor (Word 1) 2-8 Receive Completion Descriptor (Word 2) 2-9 Receive Completion Descriptor
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 x BaseClass Register 7-10 Cache Line Size Register 7-10 Latency Timer Register 7-10 Header Type Register 7-11 BIST Register 7-11 Base Address 0 Register 7-11 High Base Address 0 Register 7-12 Base Address 1 Register 7-12 Configuration
Tables Table 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 7-65 7-66 7-67 7-68 7-69 7-70 7-71 7-72 7-73 7-74 7-75 7-76 7-78 7-79 7-80 7-81 7-82 7-83 7-84 7-85 7-86 7-87 7-88 7-89 7-90 7-91 7-92 7-93 7-94 7-95 7-96 TxDmaStatus2 Register 7-42 TransmitFrameControlStatus Register 7-42 CompQueueHighAddress Register 7-43 TxCompletionQueueCtrl Register 7-43 RxCompletionQueue1Ctrl Register 7-44 RxCompletionQueue2Ctrl Register 7-45 CompletionQueueConsumerIndex Register 7-46 CompletionQueueProducerIn
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table xii 7-97 7-98 7-99 7-100 7-101 7-102 7-103 7-104 7-105 7-106 7-107 7-108 7-109 7-110 7-111 7-112 TxNibbleCnt Register 7-76 TxByteCnt Register 7-76 ReTxCnt Register 7-77 RandomNumGen Register 7-77 MskRandomNum Register 7-78 TotalTxCnt Register 7-78 RxByteCnt Register 7-79 TxPauseTimer Register 7-79 VLANType Register 7-79 MIIStatus Register 7-80 External PHY Address Examples 7-81 Address Filtering Memory 7-82 MAC Statistic Register 7-84 Transmit F
▼ ▼ ▼ ▼ 1 Introduction The Adaptec AIC-6915, PCI 10/100 Ethernet LAN Controller provides advanced Ethernet adapter features in a single chip optimized for high-performance and cost effective Ethernet NICs (Network Interface Cards). The AIC-6915 integrates all the functions necessary for an Ethernet PCI adapter to directly connect (via a Medium Independent Interface (MII) -based PHY and line transformer) to Category 5 unshielded twisted pair (UTP) or shielded twisted pair (STP).
AIC-6915 Ethernet LAN Controller Programmer’s Manual Features General ■ Supports four general purpose I/Os that can be programmed separately as inputs, outputs, open-drain outputs or, interrupt inputs ■ Interface to an external, 8-bit Boot ROM with a maximum size of 256-KByte ■ Supports dynamic system bus (PCI) clock where the network can continue to operate at any clock frequency ■ Internal loopback on all network ports for testing purposes ■ IEEE 1149.
Introduction ■ Supports 32- and 64-bit addressing of Host DMA buffers and DMA descriptor queues ■ Big/Little endian support for data and descriptors ■ Special output pin to indicate high-priority PCI request Internal Buffer Management ■ Large, 8 KByte DMA FIFO (default - 4KByte for transmit, 4-KByte for receive) ■ Programmable hardware-controlled transmit FIFO thresholds to prevent underrun of transmit FIFO and enhance overall system performance ■ Unlimited (limited only by the FIFO size) Receiv
AIC-6915 Ethernet LAN Controller Programmer’s Manual – Memory Write And Invalidate 1-4 ■ Supports PCI bus address and data parity generation and checking ■ Supports PCI PERR and SERR requirements ■ Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers ■ Supports external Boot ROM access from memory or Expansion ROM address space ■ Supports an external serial EEPROM for downloading chip configurations and MAC address ■ INTA_ interrupt generati
Introduction Block Diagram Figure 1-1 is a block diagram of the AIC-6915. Status (Receive) (Transmit) MAC Data (8) Status Station Address TCP Checksum Wakeup Data (8) Statistics TxFrame Receive Clock Status Sync. FIFO Bus (32-bits) RxFrame Arbiter TCP Checksum TxDMA 8 KByte SRAM Control Combined Tx/Rx FIFO Serial EPROM RxDMA EPROM Port DMA Bus (64-bits) Comp.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Modules The AIC-6915 contains the following major modules: ❒ 1-6 ■ PCI - Controls access to the PCI bus and contains PCI-specific registers. ■ BusAccessControl - Arbitrates master accesses to the PCI bus from internal modules, and accesses the FIFO from the PCI side. ■ SlaveAccess - Drives the REGBUS to access the internal modules when AIC-6915 is accessed from the PCI bus.
▼ ▼ ▼ ▼ 2 Receive Architecture Features The host-related Receive Architecture features are ■ Interrupts may be delayed so that only one interrupt is generated when a group of frames is received ■ Choice of shared or separate completion lists for receive and transmit.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ■ VLAN support: – Address filtering based on VLAN – Ability to delete VLAN tag and number from frame returned to the host ■ Optional second buffer list for allocating two different buffer sizes Host Data Structures Figure 2-1 illustrates the AIC-6915 receive data structures.
Receive Architecture A programmable number of words can be skipped between buffer descriptors. This allows the driver to store data related to a buffer. When using 64-bit addressing, all descriptor and completion queues must be contained in the same 32-bit address space. Descriptor queues must be aligned to a 256-byte boundary. When using 64-bit addressing, each receive buffer must fit within one 32-bit address space and must not cross a 4-GByte boundary.
AIC-6915 Ethernet LAN Controller Programmer’s Manual 32-bit Addressing Mode Table 2-1. Receive Buffer Descriptor (One-size, 32-bit Addressing) 31 24 23 16 15 8 7 Address 0 E V 64-bit Addressing Mode Table 2-2. Receive Buffer Descriptor (One-size Buffer, 64-bit Addressing) 31 24 23 16 15 8 7 LowAddress 0 E V HighAddress Descriptor Fields: ■ Address - The address of the buffer. ■ LowAddress - Least-significant 32-bits of address. ■ HighAddress - Most-significant 32-bits of address.
Receive Architecture Accepting frames The AIC-6915 uses two criteria when deciding whether to accept a frame: Frame address and frame quality. When receiving a frame, the Station Address block evaluates a frame’s address to determine if this station should receive the frame. Address filtering is accomplished by the time 64bytes are received.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 2-3. Short (Type 0) Completion Entry 31 24 0 1 Status1 23 16 15 8 EndIndex 7 0 Length Table 2-4. Basic (Type 1) Completion Descriptor 31 24 0 1 Status1 23 16 15 8 EndIndex 7 0 Length Status2 VLAN ID Table 2-5. Checksum (Type 2) Completion Descriptor 31 24 0 1 Status1 23 16 15 8 EndIndex 7 0 Length Status2 Partial TCP/UDP Checksum Table 2-6.
Receive Architecture Table 2-7. Receive Completion Descriptor (Word 0) Bit(s) Description/Function Status1 field 29 OK - The frame is good. There were no CRC errors, dribble nibble, illegal lengths, or receive code violations. In ISL mode, the ISL and Ethernet checksums must both be valid. This does not include the TCP/UDP checksum. 28 FifoFull - If set, the frame is incomplete due to FIFO full - no other status bits, except OK, are valid.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 2-8. Receive Completion Descriptor (Word 1) Bit(s) Description/Function Status2 field 31 Perfect - destination address matches one of the 16 predefined “perfect” addresses. 30 Hash - hashed destination address matches a bit set in the hash table 29 CRC Error - TRUE if the packet had a CRC error. [PE-15 CRC error] 28 ISL CRC error - TBD 27 Dribble - TRUE if the packet contains a noninteger number of bytes (i.e.
Receive Architecture Table 2-9. Receive Completion Descriptor (Word 2) Bit(s) Description/Function Partial TCP/UDP checksum field 31:16 Partial TCP/UDP Checksum - When fragmented TCP/UDP frames are received, the partial TCP/UDP checksum of the first frame is calculated by the TCP/UDP header and data. The partial TCP/UDP checksum for subsequent frames is calculated by the TCP/UDP data only VLan + Priority field 15:0 VLanID + Priority - This field contains bytes 13 and 14 of the IEEE 802.
▼ ▼ ▼ ▼ 3 Transmit Architecture Features The main features of Transmit Architecture are ■ Two Buffer Descriptor Queues in the Host Memory. One for high-priority packets and one for low-priority packets. ■ Driver notifies the transmit block to start transmitting packets by writing the “Producer Index” of descriptor queues to its internal register. Producer and consumer indices are 11-bit pointers to an 8-byte descriptor in the queue. The transmit block does not poll host memory for new packets.
AIC-6915 Ethernet LAN Controller Programmer’s Manual 3-2 ■ There are three kinds of interrupts generated by the transmit DMA engine. A “TxDmaDoneInt” is generated when the entire packet is DMA-transferred. A “TxFrameCompleteInterrupt” is generated when an entire packet is transmitted. There are two control bits, DisableTxDmaCompletion and DmaCompletionAfterTransmitComplete defined in the TxDescQueueCtrl and TxFrameControl registers to enable and disable each one of them.
Transmit Architecture ■ When the amount of packet data in the FIFO exceeds the “Transmit Threshold,” or when the end of packet is already in the FIFO, the “Transmit Frame” state machine signals the MAC to start transmitting the packet. The transmit frame block handles reading packets from the FIFO, MAC interface and FIFO link list management. It also handles “retries” in case collision occurs and handles “aborts” when MAC signals errors.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Transmit Data Structure Figure 3-1 illustrates the Transmit Data Structure Buffer Descriptors for Hi-Priority Skip Field Frame Header Pkt 1 Buf1 Pkt 1 Buf2 Pkt 1 Buf3 Skip Field Frame Header Pkt 2 Buf1 Pkt 2 Buf2 Pkt 2 Buf3 Packet Data Buffers Completion Queue Status CI Buffer Descriptors for Lo-Priority Skip Field Frame Header Pkt 3 Buf1 Pkt 3 Buf2 Pkt 3 Buf3 Host Memory High-Priority Queue Pointers CI Completion Queue Pointers CI PI PI Low-Prio
Transmit Architecture Transmit Register Set The following is a list of transmit parameters programmed by the driver during initialization. ■ Transmit descriptor queue size and base address. ■ Completion queue size and base address. ■ Descriptor type, minimum spacing, and skip field size. ■ FIFO size (4KBytes). ■ PCI cache line size. ■ DMA burst size. ■ Transmit start threshold. ■ DMA priority threshold.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 3-1. Type 0 Transmit DMA Descriptor (32-bit Addressing Only) 31 24 32 16 15 8 7 0 Skip Field (multiple of 8 bytes) One Skip Field per Packet ID = 4’b1011 I E C C N N A R T D L C R T E C N P Reserved Reserved Reserved Number Of Tx Buffers First Buffer Address Total Packet Length First Buffer Length Last Buffer Address Reserved 3-6 Last Buffer Length ■ ID: 4 bits.
Transmit Architecture Table 3-2. End Bit Functionality Desc. Type ■ Conditions Functionality Frame (0,3,4) MinFrameDescSpacing !=0 The number of bytes between two consecutive frame descriptions is fixed. The queue wraps around at the end of the fixed address. No wrap in the middle of a frame descriptor. Frame (0,3,4) MinFrameDescSpacing =0 The number of bytes between two consecutive frame descriptions is variable. For type 0/4, the queue wraps after reading 16 bytes of descriptor data.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ■ Total Packet Length: This 16-bit field defines the total packet length. If this field is zero, it is ignored and the total packet length is equal to the sum of all the buffers. If this field is nonzero, it is defined as the total packet length. Note: In Novell TCB/ECB blocks, the total packet length is not always equal to the sum of the buffer length.
Transmit Architecture Table 3-5. Type 2 Transmit DMA Descriptor (64-bit Addressing) 31 24 23 16 15 8 7 0 Skip Field (multiple of 8 bytes) One Skip Field per Buffer ID = 4’b1011 I E C C Number Of Tx Buffers N N A R (valid only if first T D L C fragment) R T E C N P Length (bytes) Reserved Low Address High Address Type 3, 32-bit Addressing Mode (Frame Descriptor) This mode is currently not supported in the AIC-6915.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 3-6.
Transmit Architecture If the AIC-6915 is programmed to transmit two words (8 bytes), the second word (bit 6332) is the InterruptStatus register content. Table 3-8. Transmit Completion Queue Entry Type = Transmit Complete Entry 31 29 28 Type 16 15 14 Transmit Status Pr i ■ Type -3 bit. Always 3’b101 for Transmit Complete Entry. ■ Transmit Status - 13 bits. The bits are defined as 0 Index Bit 12: Transmit previously paused. Bit 11: Pause control frame transmitted. Bit 10: Control frame transmitted.
▼ ▼ ▼ ▼ 4 PCI Module Architecture Features ■ Compliant with PCI Local Bus Specification, Revision 2.1 ■ Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00 and Microsoft Device Class Power Management Reference Specification (OnNow) ■ PC 97 ready. Implements all hardware features required by Microsoft’s PC 97 design specification ■ Supports 3.3V and 5.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ■ Supports PCI PERR and SERR requirements. ■ Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers. ■ Supports external Boot ROM access from memory or Expansion ROM address space. ■ Supports an external I2C serial EEPROM for downloading chip configurations and MAC address.
PCI Module Architecture PCI Block Diagram Figure 4-1 is a PCI block diagram. PCI_PADS PCI Module PCI_TOP BUFOUTFLOPS/OUTFLOPS PCITGT PCIMST EEPROMCNTL TGTDPU Pcimaster Logic Serial EPROM Datapath Logic TGTCTL control logic BOOTROMCTL DECODER BAC RX DMA Memory Port Interface Address Decoder Bus Access Control Data Fifo TX DMA SAC Slave Access Ctl Ethernet Control Module Figure 4-1.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI Master Module The PCI master transfers data to/from system memory. Therefore, the AIC-6915 never generates PCI transactions for Interrupt Acknowledge, Special Cycle, I/O space, or Configuration space. The PCI master generates all Memory space commands, and uses the optional ones as appropriate to make efficient use of cache-oriented memory hardware.
PCI Module Architecture 64-bit PCI Bus Master The AIC-6915 supports a 64-bit PCI bus master and performs 64-bit data transfers with a 64-bit target. If the responding target is a 32-bit device, the lower 32-bit of address bus is used. The REQ64_ signal is used to determine whether the system supports a 64-bit data path. A pull-up resistor on the motherboard places the PCI bus in 32-bit mode by default.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Arbitration The AIC-6915 drives AD[31:00] during 32-bit transfers and AD[63:0] during 64-bit transfers. CBE[3:0]_ are asserted on the first PCLK when GNT_ is sampled asserted and the PCI bus idle. PAR and PAR64 are asserted one PCLK later. The AIC-6915 also asserts FRAME_ and REQ64_ for 64-bit transfers if PREQ_ is asserted to start a DMA transfer. The assertion of PREQ_ indicates to the PCI System board arbiter that a master desires use of the bus.
PCI Module Architecture The value of BR_A1 pin is sampled when PCI reset is active to determine if the serial EPROM data (BR_A1=1) or the default values (BR_A1=0) should be used for ■ Vendor ID [7:0] ■ Vendor ID [15:8] ■ Device ID [7:0] ■ Device ID [15:8] ■ Sub Class [7:0] ■ Base Class [7:0] ■ SubSystem Vendor ID [7:0] ■ SubSystem Vendor ID [15:8] ■ SubSystem Device ID [7:0] ■ SubSystem Device ID [15:8] ■ Interrupt Pin [7:0] The target does not support data bursts.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Power Management The PCI bus power management defined four power states. D0 indicates the “On” state, D3 indicates the “Off” state, and D1 and D2 represent power managed states. In the AIC-6915, three states are supported. D0 and D3 are required states and D2 is an optional state. Table 4-1 shows the states supported by the AIC-6915. Table 4-1.
PCI Module Architecture CardBus CardBus is the interface between a PC card and a portable device which has 32-bit bus mastering capability. The CardBus interface is based on the PCI interface with lower power consumption, additional signals and registers supported. There are four 32-bit CardBus registers.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 4-2 lists all 16 PCI commands and the corresponding AIC-6915 response. Table 4-2. Target Response to PCI Commands CBE[3:0]_ 4-10 Command Abbrev. AIC-6915 Response to Command 0000 Interrupt Acknowledge Ignored 0001 Special Cycle 0010 I/O Read IORD Supports IORD from the IndirectIoDataPort and IndirectIoAddress registers.
PCI Module Architecture Table 4-2. Target Response to PCI Commands (Continued) CBE[3:0]_ Command Abbrev. AIC-6915 Response to Command 1011 Configuration Write CWRC Supports CWRC accesses for all registers in single function Configuration register space. Any combination of CBE[3:0]_ values is acceptable for writing bytes. When no signal is asserted the data cycle is treated as a NOP. DEVSEL_ is asserted using medium speed target response timing.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Expansion ROM Address Space When in target mode, the AIC-6915 allows access to an 8-bit ROM/EEPROM (connected to the External Memory Interface port) through the expansion ROM address space. The AIC-6915 uses positive address decoding over EXROMCTL register (stored value), AD[31:02], CBE[3:0]_ (command) and FRAME_ to obtain the doubleword access decode and claim the transaction by asserting (DEVSEL_ = medium speed).
PCI Module Architecture PERR_ The AIC-6915 asserts PERR_ for detected data parity errors only if PERRESPEN is asserted. As a target device, the AIC-6915 asserts PERR_ and sets the DPE bit active (STATUS register in PCI Configuration header) for write cycles in which it detects a data parity error, only if it claims the access and asserts DEVSEL_. PERR_ is asserted for one PCLK period for each detected error two PCLK periods after the Data phase that contained the error.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Illegal Behavior As a target, when the AIC-6915 accepts a cycle (I/O, memory, configuration) which is addressed to it and drives DEVSEL_, it checks the legality of the transaction and aborts under any of the following conditions: ❒ 4-14 ■ The combination of CBE[3:0]_ in an I/O cycle does not match the address. The AIC-6915 aborts the cycle and sets the ILLEGALBE bit in PCIDEVICESTS register.
▼ ▼ ▼ ▼ 5 Frame Processor Architecture Features ■ Calculate the TCP and UDP checksum ■ Decode frame type (TCP, UDP, ARP, RARP, IPX, Wake-up, VLAN 802.1q, Ipv4, Ipv6, ICMP, Ethernet 2, IEEE 802/803) ■ Process Ethernet 2, 802, IPv4, IPv6, TCP and UDP headers ■ Process receive data on-the-fly.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ■ LC= 0, 1 or 2, and EXCONCLOCK is set, or ■ Read/Write instruction is executed and the Input IOREADY is sampled asserted. Note: EXCONCLOCK is a bit in the instruction. The loop counter is decremented by 2 every clock cycle if EXCONCLOCK=1, or if DATAVALID is asserted. The loop counter stops when reaching its terminal count of zero. Decrementing the counter by 2 each time assures that incoming data is on a byte boundary.
Frame Processor Architecture GFP Address Space A total of 256 address locations can be accessed by the GFP executing Read/Write instructions. The target address is presented in the BRANCHADD[7:0] field of the instruction. When executing a read or write instruction, the GFP asserts GIFPRD/GFPWR, and drives GFPADD[7:0], then waits for GFPIOREADY signal to complete the execution. The total address space is divided in two. The first half, 7Fh-00h, is used for accessing external registers.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 5-1. Status/Control Register (Continued) Bit Description 16 StopTxDma - If set, indicates the transmit DMA engine must freeze its operation and wait for software intervention 17 VlanFrame - If set, indicates a VLAN 802.1q frame 18 DiscardFrame - If set, indicates the frame being processed must be discarded (transmit or receive) 19 PartialChecksumValid - If set, indicates that Wreg1 stores a valid partial checksum for a fragmented frame.
Frame Processor Architecture Block Diagram DataValid Frame Data Counter Instruction Memory Data 8 Input Mux Barrel Shifter Mask Control IP 8 Input Mux Mask Control Instruction LC Data WR1 WR2 WR3 WR4 Frame Data Figure 5-1 is a block diagram of the Data Processing Unit. ALU-Out[31:0] Simple ALU: Adder, Comparator WR1[31:0] WR2[15:0] WR3[15:0] Flag Loop Counter (LC[15:0]) Instruction Ptr Register Input2 Immediate BranchAdd Branch Logic Input1 WR4[15:0] Figure 5-1.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Instruction Formats Table 5-2 describes the Instruction Formats. Table 5-2.
Frame Processor Architecture Table 5-2. Instruction Formats (Continued) Name Bit Number Description Opcode A 3:0 CheckIpv6NextHeader - Special instruction for checking the Next Header field.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 5-2. Instruction Formats (Continued) Name Bit Number Description Opcode E 3:0 Return - Return to main program. When branching from the main program, the next instruction pointer value of the main program is saved in a special register. When executing this command, the information stored in the special register is used as the next instruction address.
Frame Processor Architecture Table 5-2.
▼ ▼ ▼ ▼ 6 AIC-6915 Internal Registers Summary For the following registers, the ‘Byte Address’ indicates each registers location in memory space given as a byte offset address from the start of the memory space dedicated for internal registers - 0x50000h. PCI Configuration Header Registers Summary The PCI configuration registers are mapped to Memory Base Address+0x50000 in memory space, 0x00 in configuration spaces and address 0x00 in I/O space.
AIC-6915 Ethernet LAN Controller Programmer’s Manual AIC-6915 Functional Registers Summary Mapped to address range 0x50040-0x500FF in memory space, address 0x40-0xFF in configuration space and address 0x40-0xFF in I/O space. These registers are read/write and can be accessed using Memory, I/O, and Configuration commands. Table 6-2.
AIC-6915 Internal Registers Summary Table 6-2.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Additional PCI Registers Summary Mapped to address range 0x50FFF-0x50100 in Memory space. These registers can be accessed using memory or indirect I/O commands. Table 6-3.
AIC-6915 Internal Registers Summary Table 6-4.
▼ ▼ ▼ ▼ 7 Register Descriptions Overview This section includes all the registers required for controlling, programming, and operating the AIC-6915. All registers throughout this section subscribe to the following format. Table 7-1. Shade Legends These bits or fields are under software control. They may be programmed by software to initialize the controller or to optimize performance. 1248 These bits or fields are used solely by the hardware.
AIC-6915 Ethernet LAN Controller Programmer’s Manual AIC-6915 Address Space A device on a PCI bus can be accessed using different PCI command types. The AIC-6915 can be accessed using Memory, I/O and Configuration commands. The 512-KByte address space is mapped to a base address defined by the operating system at boot time. The first 256-KBytes are also mapped to the expansion ROM space.
Register Descriptions 64K Internal Registers Address Map 0xFFFF Reserved 0xE000 Ethernet FIFO Access 0xC000 512K PCI Address Map Rx Frame Processor Instruction memory 0x7FFFF Reserved Tx Frame Processor Instruction memory 0x8000 Statistic register file 0x60000 0x7000 Address filtering (includes external PHY MII registers) 0x6000 (~16K words (~64KBytes)) MAC registers 0x50000 External registers 0x5000 Ethernet extra registers (16K words (64KBytes)) (PCI clock domain) 0x4000 0x40000 Physical
AIC-6915 Ethernet LAN Controller Programmer’s Manual Terminology Throughout this chapter, data values are defined as follows: ■ Byte = 8 bits ■ Halfword = 16 bits ■ Word = 32 bits ■ Doubleword = 64 bits AIC-6915 Internal Registers These registers are used by the software driver for configuration, control, and retrieval of status information. All registers which are ‘cleared on read’ are reset when the most significant bit is read.
Register Descriptions PCI Registers PCI Configuration Header Registers At the deassertion edge of the PCI reset, the AIC-6915 starts reading the serial EPROM. At the same time, the BR_A1 input is sampled.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI Command Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 04h - 05h Table 7-5. PCI Command Register 7-6 Bit(s) rw Reset Value 15:10 r 0 Always read as 0. 9 r 0 MFBTBEN: Master Fast Back-To-Back Enable. When active (=1) indicates a master can perform Fast Back-To Back transactions to different PCI targets. The AIC-6915 does not support this feature and MFBTBEN always reads zero.
Register Descriptions Table 7-5. PCI Command Register (Continued) Bit(s) rw Reset Value 0 r/w 0 Description/Function ISPACEEN: I/O Space Enable. Setting this bit enables the AIC-6915 to respond to PCI I/O transactions. When ISPACEEN is inactive the AIC-6915 does not respond to I/O cycles. PCI Status Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 06h - 07h The STATUS register is used to record status information for PCI bus related events.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-6. PCI Status Register (Continued) Bit(s) rw Reset Value 11 r/w 0 Description/Function STA: Signal Target Abort is set by the target of a PCI bus transaction if it is unable to respond due to a fatal error condition. STA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 11 (=1). The AIC-6915 indicates target-abort for the following conditions: Illegal Overlap. Illegal Write.
Register Descriptions PCI DEVREVID (Device Revision ID) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 08h Table 7-7. Device Revision ID Register Bit(s) Reset Value rw 7:0 r 03h Description/Function DEVREVID[7:0]: Always read as 3h or higher. The Device Revision ID identifies the revision level of a PCI device. Device Revision values change in metal only.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI Baseclass Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Bh Table 7-10. BaseClass Register Bit(s) rw Reset value 7:0 r 02h Description/Function BASECLASS[7:0]: The BaseClass register identifies which base class the PCI device has been assigned to. The BASECLASS for the first version of the AIC-6915 is identified as 02h (Network controller).
Register Descriptions PCI Hdrtype (Header Type) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Eh Table 7-13. Header Type Register Bit(s) rw Reset Value 7 r 0 HDRTYPE[7]: The AIC-6915 is a single function device 6:0 r 0 HDRTYPE[6:0]: Always read 0. Description/Function BIST (Built-in Self Test) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Fh Table 7-14.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI HighBASEADR0 (Base Address 0) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 14h - 17h Note: When an access is made to an address that is mapped and enabled in both the BASEADR0 and EXROMCTL registers, the PCI responds with a target abort. Table 7-16.
Register Descriptions PCI SubSystemVendor ID Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 2Ch - 2Dh Table 7-19. SubSystemVendor ID Register Bit(s) rw Reset Value 15:0 r 9004h Description/Function SubSystemVendorID[15:0]: The PCI SubSystem Vendor Identifier register helps to identify the vendor of the add-in board even though the PCI controller has been designed by another vendor and has another Vendors ID.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-21. Expansion ROM Control Register Bit(s) rw Reset Value 31:18 r/w 0 EXPROMCTL[31:18]: Indicates the mapping increment capability of 256-KBytes. 17:11 r 0 EXPROMCTL[17:11]: Always read as 0. Set the maximum ROM size to 256-KBytes. 10:1 r 0 EXPROMCTL[10:1]: Reserved: Always read as 0. 0 r/w 0 EXPROMCTL[0]: External ROM Enable.
Register Descriptions PCI INTPINSEL (Interrupt Pin Select) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 3Dh Table 7-24. Interrupt Pin Select Register Bit(s) rw Reset Value 7:0 r 1h Description/Function INTPS[7:0]: The Interrupt Pin register specifies which PCI interrupt pin the device (or device function) uses. The AIC-6915, as a single function PCI device, must use INTA_ and have a default value of 1h.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI MAXLAT (Maximum Latency) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 3Fh Table 7-26. Maximum Latency Register 7-16 Bit(s) rw Reset Value 7:0 r 06h Description/Function MAXLAT[7:0]: Always read as 06h. The Maximum Latency register indicates how often the device needs to gain access to the PCI bus. The value read from the register specifies a period of time in units of 0.25 microseconds.
Register Descriptions PCI Functional Registers Definition The following registers are accessible from PCI configuration, memory and direct I/O space. PCIDeviceConfig Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 40h - 43h Table 7-27. PCIDeviceConfig Register Bit(s) rw Reset Value 31 r/w 0 EnDpeInt: Enables assertion of DPE (in PCI Configuration Header Status register) to set PCIInt.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-27. PCIDeviceConfig Register (Continued) 7-18 Bit(s) rw Reset Value 18:16 r/w 000 15 r/w 0 EnBeLogic: When this bit is set and a DMA read is active, the PCI master asserts leading and trailing data byte enables as a function of DMA address and transfer size. When the bit is reset, the PCI master always asserts all 4-byte enables for reading data from HOST memory.
Register Descriptions Table 7-27. PCIDeviceConfig Register (Continued) Bit(s) rw Reset Value 6 r/w 0 StopOnPerr: Specifies the behavior of the PCI master when a data parity error is encountered during an active DMA operation. If the bit is asserted, the PCI master stops the transfer as soon as it detects/receives a data parity error. The PCIMstDmaEn, TxDmaEn and RxDmaEn bits are reset, and driver software intervention is required to resume operation.
AIC-6915 Ethernet LAN Controller Programmer’s Manual BacControl Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 44h - 47h This register provides the software driver a way to configure and control BAC DMA operation. Table 7-28. BacControl Register rw Reset Value 31:22 r 0 Reserved: Always read as 0. 7:6 r/w 0 DescSwapMode[1:0]: Must always be 0. 5:4 r/w 0 DataSwapMode: Controls the way transmit/receive DMA data is read and written to and from host memory.
Register Descriptions Table 7-28. BacControl Register (Continued) Bit(s) rw Reset Value 1 r/w 0 PREFERRXDMAREQ: Controls BAC’s arbitration algorithm. If the bit is set and PREFERTXDMAREQ is cleared, the receive DMA request has priority over transmit DMA data request, otherwise if both bits are cleared, they have equal (round-robin) priority. Note, the AIC-6915 implements an internal dynamically changing control signal that can force PREFERRXDMAREQ to ‘1’.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCIMonitor2 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 4Ch - 4Fh Table 7-30. PCI Monitor2 Register Bit(s) rw Reset Value 31:16 r 0 PCIMasterBusUtilization: Provides a count of the total number of PCI clock cycles that the AIC-6915 asserts PCI_FRAME_ as an active PCI master, measured from the time the software driver resets the register. The count is presented in; 1 unit=64PCIClkCycles.
Register Descriptions Table 7-31. Power Management Register (Continued) Bit(s) rw Reset Value 18:16 r 1h PMVersion: This field indicates that there are 4 bytes of General Purpose Power Management registers implemented as described in revision 1.0 of the ‘PCI Bus Power Management Interface Specification’. 15:8 r 00h NextItemPtr: This field provides an offset into the function’s PCI configuration space pointing to the location of next item in the function’s capability list.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PME Event Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 58h- 5Bh Table 7-33. PME Event Register Bit(s) rw Reset Value 31:6 r 0 Reserved: Always read 0. 5 r/w 0 ExtPhyReset: This bit controls the PHYRESET pin directly. Setting EXTPHYRESET is the only way to assert the external pin. 4 r 0 LinkFailStatus: Indicates there is a link fail.
Register Descriptions EEPROM Memory Definition Table 7-35.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCIComplianceTesting Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 64h - 67h This register is used for PCI compliance checker testing purposes only and has no meaning to the AIC-6915.. Table 7-36. PCIComplianceTesting Register Bit(s) rw Reset Value 31:0 r/w 0 Description/Function PCI compliance data word.
Register Descriptions Ethernet Registers The following registers are accessible from PCI configuration, memory, and direct I/O space. They are all synchronized to the Ethernet Transmit clock. General Ethernet Functional Registers GeneralEthernetCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 70h - 73h Table 7-39. GeneralEthernetCtrl Register Bit(s) rw Reset value 31:10 r 0 Reserved: Always reads 0. 9 r/w 0 Reserved: Always reads 0.
AIC-6915 Ethernet LAN Controller Programmer’s Manual TimersControl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 74h - 77h Table 7-40. TimersControl Register 7-28 Bit(s) rw Reset value 31 r/w 0 EarlyRxQ1IntDelayDisable: When set, the interrupt masking timer has no effect on EarlyRxQ1Int. 30 r/w 0 RxQ1DoneIntDelayDisable: When set, the interrupt masking timer has no effect on RxQ1DoneInt.
Register Descriptions Table 7-40. TimersControl Register (Continued) Bit(s) rw Reset value 12 r/w 0 RxHiPrBypass: If this bit is set, bypass the interrupt masking timer when generating RxDoneInt after DMA-transferring the completion descriptor of a high-priority frame. 11 r/w 0 Timer10X: Enables the software to easily scale the TimerClock period by a factor of 10 to match a 10 Mbits/sec or 100 Mbits/sec environment.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-40. TimersControl Register (Continued) Bit(s) rw Reset value 4:0 r/w 0 Description/Function IntMaskPeriod: Specifies a minimum amount of time between two consecutive assertions of external PCI interrupt (PCI_INTA_) as a result of the interrupt status bits TXDONEINT and RXDONEINT, if the corresponding bits TXDELAYDISABLE and RXDELAYDISABLE are at their reset state, ‘0’.
Register Descriptions InterruptStatus Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 80h - 83h This register stores the interrupt vector which indicates the interrupt source. Some of the bits in the register are cleared on a read, while others must be cleared at the source. All ‘cleared by read bits’ are also cleared when writing a ‘1’ to the bit.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-42. InterruptStatus Register (Continued) 7-32 Bit(s) rw Reset Value 19 r/w 0 DmaErrInt: This bit is set on a DMA error. The DMA errors are: Target abort, Master abort, Data parity error (with STOPONPARERR bit set), and bad descriptor. This bit is cleared on a read, or by writing a ‘1’.
Register Descriptions Table 7-42. InterruptStatus Register (Continued) Bit(s) rw Reset Value 10 r/w 0 EarlyRxQ1Int: This bit is set after the DMA transfer of a programmable number of bytes of a received frame. The programmable number is defined by RxEarlyIntThreshold. No status is DMA-transferred at this time. The RxQ1DoneInt interrupt is generated when the whole frame is DMA-transferred. At this time EarlyRxQ1Int is cleared. This bit is cleared on a read, or by writing a ‘1’.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ShadowInterruptStatus Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 84h - 87h This register is used for reading the Interrupt Status register in read-only mode. In this mode the interrupt status bits that are defined as ‘cleared by read’ are not affected. Table 7-43.
Register Descriptions InterruptEn Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 88h - 8Bh Specifies if the corresponding bit in INTERRUPTSTATUS register is enabled, causing an external PCI interrupt. The PCI interrupt bit must be enabled in the PCIDEVICECONFIG register. Table 7-44.
AIC-6915 Ethernet LAN Controller Programmer’s Manual GPIO Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 8C - 8Fh The GPIO register provides for host software control of the GPIO[3:0] pins. Table 7-45. GPIO Register Bit(s) 7-36 rw Reset Value Description/Function 31:28 r 0 27:24 r/w 1111 Reserved: Always written as ‘0’. 23:20 r 0 Reserved: Always written as ‘0’.
Register Descriptions Transmit Registers TxDescQueueCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 90h - 93h Table 7-46. TxDescQueueCtrl Register Bit(s) rw Reset Value 31:24 r/w 2 TxHighPriorityFifoThreshold: Specifies a programmable threshold.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-46. TxDescQueueCtrl Register (Continued) Bit(s) rw Reset Value 6:4 r/w 0 MinFrameDescSpacing: Defines the minimum number of bytes between two consecutive frame/buffer descriptors. This feature is particularly useful for operating systems that have a variable number of fragments per frame (Netware). ‘000’ - not restricted ‘001’ - 32 byte ‘010’ - 64 byte ‘011’ - 128 byte ‘100’ - 256 byte all other combinations are reserved.
Register Descriptions HiPrTxDescQueueBaseAddr Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 94h - 97h Table 7-47. HiPrTxDescQueueBaseAddress Register Bit(s) rw Reset Value 31:8 r/w 0 HighPriorityTxDescQueueBaseAddress[31:8]: When written with a nonzero value, this field indicates the starting address of the queue in host memory. It is written by the software driver during device initialization. The address must be aligned to a 256-byte boundary.
AIC-6915 Ethernet LAN Controller Programmer’s Manual TxDescQueueHighAddr Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 9Ch - 9Fh Table 7-49. TxDescQueueHighAddr Register Bit(s) rw Reset Value 31:0 r/w 0 Description/Function TxDescQueueHighAddr[31:0]: Contains the upper 32-bits of address of the transmit descriptor queues when using 64-bit addressing.
Register Descriptions TxDescQueueConsumerIndex Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: A4h- A7h Table 7-51. TxDescQueueConsumerIndex Register Bit(s) rw Reset Value 31:27 r 0 Reserved: Always read as ‘0’. 26:16 r 0 HiPrTxConsumerIndex: Written by the AIC-6915 and read by the software driver. This field points to an 8-byte entry in the low-priority DMA descriptor queue.
AIC-6915 Ethernet LAN Controller Programmer’s Manual TxDmaStatus2 Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: ACh- AFh Table 7-53. TxDmaStatus2 Register Bit(s) rw Reset Value 31:29 r 0 FragmentCount: Specifies the number of buffer fragments that still have to be DMA-transferred in order to complete fetching of the entire frame. 28:16 r 0 FifoWritePointer: Current FIFO write pointer from transmit DMA.
Register Descriptions Completion Queue Registers Note: All completion queues have a fixed size of 1KByte entries. CompletionQueueHighAddr Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: B4h - B7h Table 7-55. CompQueueHighAddress Register Bit(s) rw Reset Value 31:0 r/w x Description/Function CompQueueHighAddr[31:0]: Upper 32-bits of address of all the completion queues.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-56. TxCompletionQueueCtrl Register (Continued) Bit(s) rw Reset Value 4 r/w 0 CommonQueueMode: When this bit is set, the receive completion queues are disabled and all completion descriptors and general chip status are DMA-transferred to the Transmit Completion Queue. This bit overrides any values specified for the receive completion queues. In this mode the maximum receive completion size is 8-bytes.
Register Descriptions Table 7-57. RxCompletionQueue1Ctrl Register (Continued) Bit(s) rw Reset Value 3:0 r/w 0 Description/Function RxCompletionQ1Threshold specifies a threshold equal to 4*RxCompletionQ1Threshold. If RxCompletionQ1ThresholdMode is ‘0’ and the number of empty entries in receive queue 1 is less or equal to the threshold, an interrupt status bit is set.
AIC-6915 Ethernet LAN Controller Programmer’s Manual CompletionQueueConsumerIndex Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: C4h - C7h Note: A queue is considered empty if both QUEUEPRODUCERINDEX and QUEUECONSUMERINDEX are equal. The queue is considered full if the value of QUEUEPRODUCERINDEX + 1 is equal to the value of QUEUECONSUMERINDEX. If the corresponding COMPLETIONSIZE bit is cleared, the index points to a 4-byte address.
Register Descriptions CompletionQueueProducerIndex Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: C8h - CBh Table 7-60. CompletionQueueProducerIndex Register Bit(s) rw Reset Value 31:26 r 0 Reserved: Always read and written as zero. 25:16 r/w 0 TxCompletionProducerIndex: Written by the AIC-6915 and read by the host driver.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-61. RxHiPrCompletionPtrs Register (Continued) Bit(s) rw Reset Value 9:0 r/w 0 Description/Function RxCompletionQ2ConsumerIndex: Written by software driver and read by the AIC-6915. The software driver increments or writes a new index to free space in the queue. Receive Registers RxDmaCtrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: D0h - D3h Table 7-62.
Register Descriptions Table 7-62. RxDmaCtrl Register (Continued) Bit(s) rw Reset Value 22:20 r/w 0 RxDmaQueueMode[2:0]: This field determines how to select the DMA buffer descriptor queue. The encoding is as follows: ‘000’ - Disable buffer descriptor queue 2. DMA all (good) packets to buffers taken from queue 1. ‘001’ - DMA all (good) packets to buffers taken from queue 1. Queue 2 is only used if chosen by the frame processor.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-62. RxDmaCtrl Register (Continued) Bit(s) rw Reset Value 11:8 r/w 6h RxHighPriorityThreshold[3:0]: If more than RxHighPriorityThreshold * 256 ± 128 bytes are in the FIFO, increase the priority of receive DMA requests. The high-priority indication is used by the internal arbiter (BAC) to determine which module (transmit or receive) to service next. The programmable threshold in bytes is 16 * RXHIGHPRIORITYFIFOTHRESHOLD.
Register Descriptions Table 7-63. RxDescQueue1Ctrl Register (Continued) Bit(s) rw Reset Value 13 r/w 0 RxVariableSizeQueues: Indicates the Rx descriptor mode: ‘0’ - Fixed size queue is used. ‘1’ - Variable size queue is used. If the descriptor queue is variable size, it still has a maximum of 256 or 2048 entries depending on RXDESCQUEUESIZE.
AIC-6915 Ethernet LAN Controller Programmer’s Manual RxDescQueue2Ctrl Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: D8h - DBh Table 7-64. RxDescQueue2Ctrl Register Bit(s) rw 31:16 r/w Reset Value Description/Function RxQ2BufferLength[15:0]: Indicates the length of buffer in bytes. This value must be an integral number of 4-byte words. 15 r 0 Reserved: Always written with zero.
Register Descriptions Table 7-66. RxDescQueue1LowAddress Register (Continued) Bit(s) rw Reset value 7:0 r 0 Description/Function Reserved: Always write 0 RxDescQueue2LowAddress Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: E4h - E7h Table 7-67.
AIC-6915 Ethernet LAN Controller Programmer’s Manual RxDescQueue2Ptrs Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: ECh - EFh Table 7-69. RxDescQueue2Ptrs Register Bit(s) rw Reset Value 31:27 r/w 0 Reserved: Always write 0. 26:16 r/w 0 RxDescQ2Consumer: Written by the AIC-6915 and read by host. This field indicates the address of the last descriptor read by the AIC-6915.
Register Descriptions RxAddressFilteringCtrl Register Address filtering, which is controlled by the RXADDRESSFILTERINGCTRL register and various address filtering memories, determines which frames are accepted by the AIC-6915 and passed to the driver. The frame’s destination address is compared against the following three criteria. If the address matches any of these criteria, the frame is accepted.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-71. RxAddressFilteringCtrl Register 7-56 Bit(s) rw Reset Value 31:16 r/w 0 PerfectAddressPriority[15:0]: Each bit in this field corresponds to one “perfect” address, bit 0 corresponding to the first address.
Register Descriptions Table 7-71. RxAddressFilteringCtrl Register (Continued) Bit(s) rw Reset Value 7:6 r/w 0 PerfectFilteringMode[1:0] ‘00’ - Perfect filtering disabled. ‘01’ - 16 perfect addresses filtering. The AIC-6915 compares the incoming frame destination address with 16 addresses stored in an internal SRAM, then DMA transfers the frame if there is a match. ‘10’ - 16 perfect addresses inverse filtering.
AIC-6915 Ethernet LAN Controller Programmer’s Manual RxFrameTestOut Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: F8h- FBh Table 7-72. RxFrameTestOut Register 7-58 Bit(s) rw Reset Value 31:24 r 0 Reserved: Always read as 0.
Register Descriptions PCI Diagnostic Registers The following registers are accessible from PCI configuration, memory, and indirect I/O space. They are used for diagnostic purposes only. PCITargetStatus Register Type: R/W Internal Registers Subgroup: PCI Extra Registers Byte Address: 0100h - 0103h This register is for diagnostic purposes only. When the AIC-6915 responds with a target abort, the software driver can determine the reason by reading this register. Table 7-73.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCIMasterStatus1 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0104h - 0107h This register is used for diagnostic purposes to read the internal status of a DMA operation. Table 7-74. PCIMasterStatus1 Register 7-60 Bit(s) rw Reset Value 31:25 r 1 PCIRequestState: Provides the current state of the PCI master request state machine. The total number of states is 7 each state is represented by 1 bit.
Register Descriptions PCIMasterStatus2 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0108h-010Bh Table 7-75. PCIMasterStatus2 Register Bit(s) rw Reset Value 31:26 r 0 Reserved: Always read as 0. 25 r x System64: Provides the information of the system: Setting the bit indicates a 64-bit system, while clearing the bit indicates a 32-bit system. 24:10 r 1 PCIMainState: Provides the current state of the PCI master main state machine.
AIC-6915 Ethernet LAN Controller Programmer’s Manual BacDmaDiagnostic0 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0110h - 0113h Table 7-77. BACDMADiagnostic0 Register Bit(s) rw Reset Value 31:29 r 0 Reserved: Always read as 0. 28:16 r X StartFifoPtr[12:0]: This is a tri-state bus that contains the start value of the FIFO pointer of the current DMA transfer. This value is driven by the DMA requester and is stable until another DMA requester is granted.
Register Descriptions BacDmaDiagnostic2 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0118h - 011Bh This register provides information about the current DMA transfer and is used for diagnostic purposes only. All values in the register are synchronized to the Ethernet clock. Table 7-79. BacDmaDiagnostic2 Register Reset Value Bit(s) rw Description/Function 31:29 r 0 28:16 r 1X 15:13 r 0 Reserved: Always read as 0.
AIC-6915 Ethernet LAN Controller Programmer’s Manual BacDmaDiagnostic3 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 011Ch - 011Fh Table 7-80. BACDMADiagnostic3 Register 7-64 Bit(s) rw Reset Value 31:25 r 0 Reserved: Always read as 0. 24 r 0 IllegalDmaReq: This bit is set during a receive DMA request when the host address is not aligned on a (32-bit) word boundary. 23 r 0 TxDmaReq: Is the fifth highest priority DMA request line.
Register Descriptions MacAddr1 Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 0120h - 0123h Table 7-81. MacAddr1 Register Bit(s) rw Reset Value 31:0 r/w 0 Description/Function MacAddr[31:0]: The MAC address of the AIC-6915 is read from the external serial EPROM and loaded in to the MACADDR register. The software driver can overwrite the value by writing to this register.
AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI CardBus Registers The following registers are defined in the CardBus PC Card Electrical Specification. Their implementation in the AIC-6915 is described here. For more detailed information on the meaning of these bits see the PC Card specification. The registers are accessible from PCI memory and indirect I/O space. They are all synchronized to the PCI clock. They are usually not accessed during normal operation.
Register Descriptions FunctionEventMask Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 0134h - 0137h Controls which events cause a status change interrupt. Only bit 15 is implemented, all other bits are zero. Table 7-84. FunctionEventMask Register Bit(s) rw Reset Value Description/Function 31:16 r 0 Reserved: Always reads 0. 15 r/w* 0 Intr: Interrupt Mask. If set, and bit 15 (INTR) of the FUNCTIONEVENT register is set, an interrupt is generated.
AIC-6915 Ethernet LAN Controller Programmer’s Manual ForceFunction Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 013Ch - 013Fh Setting a bit here also sets a bit in the FunctionPresentState register. Since only the interrupt function is supported, only bit 15 is implemented. Table 7-86.
Register Descriptions Additional Ethernet Registers The following group of registers control access to the MAC, physical device (MII), transmit FP, receive FP, and Ethernet FIFO. The registers are accessible from PCI memory and indirect I/O space. They are all synchronized to the Ethernet transmit clock and are usually not accessed during normal operation. Ethernet Physical Device Registers MIIRegistersAccessPort Type: R/W Internal Registers Subgroup: MII Registers Byte Address: 2000h - 3FFFh Table 7-87.
AIC-6915 Ethernet LAN Controller Programmer’s Manual TestMode Register (TBD) Type: R/W Internal Registers Subgroup: Ethernet Extra Registers Byte Address: 4000h - 4003h This register controls test mode of the chip. Table 7-88. TestMode Register rw Reset Value 31:9 r 0 Reserved. Always reads 0. 8 r/w 0 Boot EPROM Test Select - This bit is used by the Boot EPROM control block to multiplex out test output bits instead of using regular functional output bits.
Register Descriptions MAC Control Registers MacConfig1 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5000h - 5003h Table 7-91. MacConfig1 Register Bit(s) rw Reset Value 31:16 r/w 0 Reserved: Always read as 0. 15 r/w 0 SoftRst: Software reset to internal MAC logic. This bit has no effect on any configuration register state.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-91. MacConfig1 Register (Continued) Bit(s) rw Reset Value 5 r/w 0 NoBackoff: Controls the backoff algorithm after a collision. When the bit is reset the backoff algorithm is invoked every time a collision occurs during a transmit operation. The retransmission is determined by a controlled randomization process called ‘truncated binary exponential backoff’.
Register Descriptions MacConfig2 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5004h- 5007h Table 7-92. MacConfig2 Register Bit(s) rw Reset Value 31:16 r/w 0 Reserved: Always read as 0. 15 r 0 TxCRCerr: Transmit Ethernet CRC error status. 14 r 0 TxIslCRCerr: Transmit ISL (Interswitch Link) CRC error status. 13 r 0 RxCRCerr: Receive Ethernet CRC error status. 12 r 0 RxIslCRCerr: Receive ISL CRC error status. 11 r 0 TXCF: Transmit Control Frame.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-92. MacConfig2 Register (Continued) Bit(s) rw Reset Value 2 r/w 0 TxISLEn: Enables ISL function. When this bit is cleared, regular Ethernet frames are transmitted and received. When this bit is set the ISL frame, including the encapsulated Ethernet frame, are transmitted and received.
Register Descriptions NonBkToBkIPG Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 500Ch- 500Fh Table 7-94. NonBkToBkIPG Register Bit(s) rw Reset Value 31:15 r/w 0 14:8 r/w 0Ch 7 r/w 0 Reserved: Always reads 0. 6:0 r/w 6h IPGR2: If a carrier is sensed after IPGR1 and before IPGR2 expires, the transmit engine continues to count time even though a carrier has been sensed.
AIC-6915 Ethernet LAN Controller Programmer’s Manual MaxLength Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5014h - 5017h Table 7-96. MaxLength Register Bit(s) rw Reset Value 31:16 r/w 0 15:0 r/w 1536 (600h) Description/Function Reserved: Always read as 0. MaxPacketLength: Frames longer than the specified number of bytes are truncated unless the HUGEENABLE control bit in the configuration is asserted, in which case no transmit frame length is enforced.
Register Descriptions ReTxCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5020h- 5023h Table 7-99. ReTxCnt Register Bit(s) rw Reset Value 31:4 r/w 0 Reserved: Always read as 0. 3:0 r/w 0 ReTxCnt: This counter keeps track of the number of times a retransmission has occurred. The final count is loaded in statistics vectors. It should only be written for test purposes, such as speeding up simulation time.
AIC-6915 Ethernet LAN Controller Programmer’s Manual MskRandomNum Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5028h - 502Bh Table 7-101. MskRandomNum Register Bit(s) rw Reset Value 31:10 r/w 0 Reserved: Always read as 0. 9:0 r/w 0 MskRandomNum: This is the sliding window mask result on RANDOMNUMGEN register. This mask is used to implement the truncated binary exponential backoff algorithm.
Register Descriptions RxByteCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5040h- 5043h Table 7-103. RxByteCnt Register Bit(s) rw Reset Value 31:16 r/w 0 Reserved: Always reads 0. 15:0 r/w 0 RxByteCnt: This is a multipurpose counter used internally to count the number of bytes at different times. It should only be written for test purposes, such as testing huge frame functionality.
AIC-6915 Ethernet LAN Controller Programmer’s Manual MIIStatus Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5070h - 5073h Table 7-106. MIIStatus Register 7-80 Bit(s) rw Reset value 31:5 r 0 Reserved: Always read as 0. 4 r 0 MIILink Fail: MII Link Fail indicator. Setting this bit indicates to the current PHY that the AIC-6915 is continuously scanning for link status. The external PHY’s Status register’s (Register 1) bit 2, has failed.
Register Descriptions Since each external PHY takes up 128 bytes (32 x 32 bits), the actual address offset to access each of them through the AIC-6915 is: Table 7-107.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Address Filtering Registers Perfect Address Memory Register Type: R/W Internal Registers Subgroup: Address Filtering Memory Access Byte Address: 6000h - 6FFFh Table 7-108 starts at byte address 6000h from the internal registers base address, offset 56000h from the AIC-6915’s base address. No bits have reset values, so all bits corresponding to enabled functions must be written.
Register Descriptions Table 7-108. Address Filtering Memory (Continued) byte (h) word (h) word -> 3 2 1 0 2C0 B0 Internal 463-448 463-448 2D0 B4 Internal 479-464 479-464 2E0 B8 Internal 495-480 495-480 2F0 BC Internal 511-496 511-496 Perfect Addresses The AIC-6915 compares the destination address of the incoming frame against all of the perfect addresses stored in memory. The comparison is used as one of the criteria for accepting a frame.
AIC-6915 Ethernet LAN Controller Programmer’s Manual MAC Statistic Registers Type: R/W Internal Registers Subgroup: MAC Statistic Byte Address: 7000h - 7FFFh The following are a list of statistics counters tracked by the MAC block. The “Source” field indicates the internal logic block that generates the statistics. The “Priority” field indicates 802.3 priority; “M” as mandatory, “R” as recommendation, “O” as optional. All the “M” and “R” fields are supported.
Register Descriptions Table 7-109. MAC Statistic Register (Continued) Byte Addr Source Priority 34h Frames Lost due to Internal Transmit Errors. (Cannot recover from FIFO underrun) Statistics TX R 32 Bits Count the number of frames which are lost in transmit engine because it cannot retransmit after encountering FIFO underflow errors. Descriptions 38h Receive OK Frames MAC (RX) M 32 Count the number of frames successfully received.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-109. MAC Statistic Register (Continued) Byte Addr Source Priority 6Ch Receive Packets 128 to 255 Bytes Statistics MAC (RX) RMON 32 Bits Count the number of receive frames whose length is between 128 and 255 bytes. Descriptions 70h Receive Packets 256 to 511 Bytes MAC (RX) RMON 32 Count the number of receive frames whose length is between 256 and 511 bytes.
Register Descriptions Transmit Frame Processor - TxGfpMem Type: R/W Internal Registers Subgroup: Transmit Frame Processor Register Byte Address: 8000h-9FFFh Table 7-110. Transmit Frame Processor Register Bit(s) rw Reset Value 31:0 r/w x Description/Function TxGfpMem: This field defines a 256-byte address space that the software driver can use to access the transmit General Frame Processor program memory.
▼ ▼ ▼ ▼ 8 Sample Driver The following sample driver documentation is intended as a guide for the software developer writing a device driver for the Adaptec AIC-6915 Ethernet Network Controller. It is designed to complement the driver source code in the DDK and to serve as a basic checklist for driver development. Initialization of the controller, receive and transmit queues, and interrupt handling are covered in this document.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Producer-Consumer Model for the AIC-6915 The AIC-6915 uses the Producer-Consumer model for its operation and interaction with the driver. One of the entities (AIC-6915 or the driver) "Produces" work items by placing them in a shared queue, the other entity "Consumes" the work items by dequeueing them from the queue.
Sample Driver Basic Register Initialization and Reset Sequence The first step in the initialization process is NIC recognition. The most straightforward method of finding the card is through PCI configuration space. Operating system-specific calls may be used to locate the device with the AIC-6915 Device ID (6915) and Vendor ID (9004).
AIC-6915 Ethernet LAN Controller Programmer’s Manual 1 PCI COMMAND Register (offset 04h): The PCI Command register must be initialized to enable memory and/or I/O register access, to enable bus master mode, to enable Memory Write and Invalidate, and to enable system error response. The Command register does not have to be reinitialized for a reset operation. 2 PCI HIGHBASEADR0 Register (offset 14h): For 32-bit addressing, the upper 32 bits of the memory address should be initialized to zero.
Sample Driver 8 InterruptStatus (offset 80h): The InterruptStatus register should be set to zero during initialization. There are two types of status bits - those that are cleared on read or write, and others that must be cleared at the source. 9 InterruptEnable (offset 88h): This register indicates which events should trigger an interrupt. It is application-specific, but at a minimum the following interrupts must be enabled. Required Fields: – RxQ1(2)DoneIntEn = 1: This is the normal receive interrupt.
AIC-6915 Ethernet LAN Controller Programmer’s Manual // Other fields in MacConfig1 may remain at the default value AIC6915_WRITE_REG(Adapter->RegisterBaseVa->MacConfig1, MacConfig1Value); // Read MacConfig1 again AIC6915_READ_REG(MacConfig1, MacConfig1Value); // Now do a soft reset to the MAC, separately from the programming step MacConfig1Value.
Sample Driver // Specify which interrupts we want InterruptEnValue.RxQ1DoneIntEn = 1; // interrupt on receive DMA InterruptEnValue.TxDmaDoneIntEn = 1; // interrupt on transmit DMA // The hardware is now ready to transmit and receive packets! Receive Process The receive process in the AIC-6915 is based on the use of a receive completion queue and receive buffers. Their relationship is discussed below.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Type 2 Completion Descriptor The Type 2 descriptor is also known as the checksum completion descriptor. It consists of two word entries. The first word is identical to the Type 0 descriptor. The second word contains extended status information and a partial TCP/UDP checksum. To program the AIC-6915 to use a Type 2 descriptor, the developer must set RXCOMPLETIONQ1TYPE in register RXCOMPLETIONQUEUE1CTRL to 10b.
Sample Driver Two Receive Queues The AIC-6915 offers the ability to use two Receive Completion Descriptors Queues and two Receive Buffer Descriptor Queues. Two Receive Buffer Descriptor Queues are selected through the RXDESCQUEUE2CTRL register. There is a corresponding register, RXCOMPLETIONQUEUE2CTRL, if two receive completion queues are used. Use of two completion queues does not dictate the use of two receive descriptor queues, and vice versa.
AIC-6915 Ethernet LAN Controller Programmer’s Manual 1 RXCOMPLETIONQUEUE1CTRL (offset BCh): This register is used to define the location and type of the first Receive Completion Descriptor Queue. Required Fields: – RxCompletionQ1BaseAddress: Assign the base address of Receive Completion Descriptor Queue 1 in hardware. – RxCompletionQ1Type: Select the type of the Receive Completion Descriptor. Four completion descriptor types are available.
Sample Driver 6 RXDMACTRL (offset D0h): This register controls receive DMA operation and frame acceptance criteria. Required Fields: – RxCompletionQ2Enable: Enable the second Receive Completion Descriptor Queue if needed. – RxDmaQueueMode: Select the queue sorting criteria, if a second queue is needed. Sorting may be based on packet size or priority. 7 RXDESCQUEUE1CTRL (offset D4h): This register defines Receive Buffer Descriptor Queue 1.
AIC-6915 Ethernet LAN Controller Programmer’s Manual 11 RXDESCQUEUE1PTRS (offset E8h): This register contains the consumer and producer indices for the first Receive Buffer Descriptor Queue. Initialization of this register depends on the choice of the receive model - producer-consumer versus polling. Required Fields: – RxDescQ1Consumer = 0: Initialize the consumer index to zero.
Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.
AIC-6915 Ethernet LAN Controller Programmer’s Manual // If single queue, use the first queue only // Initialize RxDescQueue1LowAddress // Allocate memory for RxDescQueue1 AIC6915_ALLOC_MEMORY(&Status, &RxDescQ, 4 * 2048); // 4 byte descriptor, //2K fixed size queue RxDescQueue1LowAddressvalue.Reserved = 0; // assign the buffer address RxDescQueue1LowAddrValue.
Sample Driver Receive Interrupt Handling When a packet is received, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue and generates either an EARLYRXQ1INT (or EARLYRXQ2INT) or an RXQ1DONEINT (or RXQ2DONEINT), depending on which receive interrupts have been enabled. When the driver processes this interrupt, it must first read the Receive Completion Queue consumer and producer indices.
AIC-6915 Ethernet LAN Controller Programmer’s Manual // RxBufferRing structure contains pointers to physical and virtual // buffer addresses, and flush buffer address CurrentRxBuffer = Adapter->RxBufferRing[RxDescIndex]; // Indicate the packet to the protocol (operating system specific).
Sample Driver transmit completion interrupt which is enabled. The Transmit Completion Descriptors are described in more detail below. Transmit Completion Descriptor Types DMA Complete Transmit Completion Descriptor This four byte descriptor contains an identifier of 100b, which denotes a DMA complete entry. It also includes a time stamp field, representing the 13 least significant bits of the 32-bit timer.
AIC-6915 Ethernet LAN Controller Programmer’s Manual of descriptor. These descriptors are outlined below. For a complete description, refer to the Transmit Architecture section. All hardware indices which reference a Transmit Buffer Descriptor are incremented by a value which is dependent upon the size of the descriptor. The size of the descriptor will vary, depending upon the descriptor type, skip field option, and number of buffers in the descriptor for Type 0 and Type 4 descriptors.
Sample Driver Transmit Producer or Consumer index to a software array index. The size of a Type 1 descriptor in bytes is calculated using the formula: (8 + SKIPFIELDBYTES). For example, assume that a Type 1 descriptor is in use, with a 16-byte skip field. The size of the descriptor is then 24 bytes. This includes 16 bytes for the skip field, 4 bytes for the ID header and 4 bytes for the buffer address.
AIC-6915 Ethernet LAN Controller Programmer’s Manual To convert the hardware Transmit Producer or Consumer index to a software index, multiply the hardware index by 8, and then divide by the calculated size of the descriptor. Refer to the Transmit DMA Buffer Descriptor Queue section in the Transmit Architecture chapter for a description of all fields in this descriptor type. Two Transmit Queues Only one Transmit Completion Descriptor Queue is available.
Sample Driver Transmit Initialization The AIC-6915 provides a set of registers which must be initialized in preparation for transmitting packets. These registers and the fields which must be initialized in the driver are summarized below. Register bits which are not explicitly described here may be left at the default reset value. The developer must determine if these default values need to be modified for the driver under development. These registers may be initialized in any order.
AIC-6915 Ethernet LAN Controller Programmer’s Manual 5 TXDESCQUEUEPRODUCERINDEX (offset A0h): This register contains the producer index for both the high and low priority Transmit Buffer Descriptor Queues. These fields are incremented in software whenever the driver has prepared a packet for transmission. The producer index is more appropriately referred to as an offset.
Sample Driver Required Fields: – RxCompletionQ1ConsumerIndex = 0: Initialize the Receive Completion Descriptor Queue 1 consumer index to zero. Note: this entry is also covered in the Receive Initialization section. – TxCompletionConsumerIndex = 0: Initialize the Transmit Completion Descriptor Queue consumer index to zero. 11 COMPLETIONQUEUE1PRODUCERINDEX (offset C8h): This register contains both the Receive and Transmit Completion Descriptor Queue producer indices.
AIC-6915 Ethernet LAN Controller Programmer’s Manual // Set up the low 32 bits of the low priority transmit descriptor queue // base address LoPrTxDescQBaseAddrValue = NdisGetPhysicalAddressLow(Adapter->TxDescRing.
Sample Driver Transmit Handling In the code fragment below, the operating system has called the transmit routine with a packet to be transmitted. The driver must set up the Transmit Buffer Descriptor(s) for all buffers in this packet, and then instruct the AIC-6915 controller to transmit the packet.
AIC-6915 Ethernet LAN Controller Programmer’s Manual Adapter->MapRegisterIndex, TRUE, PhysicalSegmentArray, &BufferPhysicalSegments); // Put each physical segment for this buffer into a Transmit Buffer // Descriptor for (ii = 0 ; ii < BufferPhysicalSegments; ii++) { PhysicalAddressUnit = PhysicalSegmentArray[ii] ; // Get a local copy of this Transmit Buffer Descriptor TxDesc = Adapter->TxDesc[CurrentTxDescIndex]; // We only fill in the NumberOfFragments field and the owning packet // for the descriptor poi
Sample Driver &CurrentBuffer); } // while (CurrentBuffer) // We’ve placed all the buffers in this packet into Transmit Buffer // Descriptors. // We’re ready to tell the chip to transmit the packet. // Advance the Tx Producer Index causing the chip to transmit the packet out. // The Producer index is incremented by units of 8 bytes. For this example, // we are using a Type 1 descriptor (8 bytes) with an 8 byte skip field.
AIC-6915 Ethernet LAN Controller Programmer’s Manual // The index is a multiple of the size of the Transmit Buffer Descriptor. IndexToDescriptor = TxCompletionDesc->ConsumerIndex/ sizeof(AIC6915_TX_DESC); TxDesc = Adapter->TxDesc[IndexToDescriptor]; // Return the packet to the operating system. // This is the packet given to us by the operating system when the // transmit was first initiated. The packet was stored in the skip field // at that time.
Sample Driver AIC-6915 DDK Features Table 8-1 is a list of the major features available in the AIC-6915 and demonstrated in the DDK. Table 8-1. AIC-6915 DDK Features Feature Status Comments Low/Hi priority Tx Buffer Descriptor Queues Option to implement one or two queues Set through #define in A6915HRD.H Low/Hi priority Rx Buffer Descriptor Queues Option to implement one or two queues Set through #define in A6915HRD.
AIC-6915 Ethernet LAN Controller Programmer’s Manual DDK Development Environment The drivers contained in the DDK were written for the Windows NT environment. There is an NDIS 3.0/4.0 driver and an NDIS 5.0 driver in the DDK. They were developed using Version 5.0 of the Microsoft Visual C++ compiler. When using this compiler version, the /Ox optimization cannot be used in a free build. Using the default optimization of /Oxs results in some incorrect code generation.
