Technical information

7-33
Register Descriptions
10 r/w 0
EarlyRxQ1Int:
This bit is set after the DMA transfer of a
programmable number of bytes of a received frame. The
programmable number is defined by
RxEarlyIntThreshold.
No
status is DMA-transferred at this time. The
RxQ1DoneInt
interrupt
is generated when the whole frame is DMA-transferred. At this time
EarlyRxQ1Int
is cleared. This bit is cleared on a read, or by writing a
‘1’.
9r/w0
RxQ2DoneInt:
Indicates that at least one complete Ethernet frame
has been DMA-transferred to host memory. The AIC-6915 sets the
bit after the DMA transfer of a receive completion descriptor to the
receive completion descriptor queue 2. This bit is cleared on a read,
or by writing a ‘1’.
8r/w0
RxQ1DoneInt:
Indicates that at least one complete Ethernet frame
has been DMA-transferred to host memory. The AIC-6915 sets the
bit after the DMA transfer of a receive completion descriptor to the
receive completion descriptor queue 1. This bit is cleared on a read,
or by writing a ‘1’.
7r/w0
RxGfpNoResponseInt:
Indicates that the receive DMA engine was
expecting the GFP to check the checksum for the frame being
received, but the GFP does not respond for at least 16 transmit
clocks.
6r/w0
RxQ2LowBuffersInt:
Indicates a shortage of receive buffers in the
receive buffer descriptors queue 2. The bit is set when the AIC-6915
tries to fetch a buffer descriptor and the number of buffers available
in the queue is less than a programmable threshold as defined in the
RxDmaCtrl
register. This bit is cleared on a read, or by writing a ‘1’.
The number of buffers in the queue is determined by the producer
and consumer indices of the queue.
5r/w0
NoTxChecksumInt:
Indicates that the transmit DMA engine was
expecting the GFP to provide the checksum for the frame being
transmitted, but the GFP either reported not being able to calculate
the checksum, or did not respond for at least 16 transmit clocks.
If the GFP terminates the program execution because it is not able to
compute the checksum, but does not request termination of the
DMA operation, the frame is transmitted normally.
4r/w0
TxLowPrMismatchInt:
Indicates that the transmit DMA engine
detected a bad ID in a low priority transmit buffer descriptor. The
expected ID is 1011b.
3r/w0
TxHiPrMismatchInt:
Indicates that the transmit DMA engine
detected a bad ID in a high priority transmit buffer descriptor. The
expected ID is 1011b.
2r/w0
GfpRxInt:
Indicates that the receive GFP has asserted the interrupt
status bit. The GFP asserts the interrupt by executing a write
instruction to address ‘0x0E’.
1r/w0
GfpTxInt:
Indicates that the transmit GFP asserts the interrupt
status bit. The GFP asserts the interrupt by executing a write
instruction to address ‘0x0F’.
0r/w0
PCIPadInt:
This bit is set if the AIC-6915 asserts the PCI bus
interrupt line.
Table 7-42. InterruptStatus Register (Continued)
Bit(s) rw
Reset
Value Description/Function