Technical information

7-35
Register Descriptions
InterruptEn Register
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: 88h - 8Bh
Specifies if the corresponding bit in
I
NTERRUPT
S
TATUS
register is enabled, causing
an external PCI interrupt. The PCI interrupt bit must be enabled in the
PCID
EVICE
C
ONFIG
register.
Table 7-44. InterruptEn Register
Bit(s) rw
Reset
Value Description/Function
31:28 r/w 0 GPIOIntEn[3:0]
27 r/w 0 StatisticWrapIntEn
26 r/w 0 Reserved
25 r/w 0 AbNormalInterruptEn
24 r/w 0 GeneralTimerIntEn
23 r/w 0 SoftIntEn
22 r/w 0 RxCompletionQueue1IntEn
21 r/w 0 TxCompletionQueueIntEn
20 r/w 0 PCIIntEn
19 r/w 0 DmaErrIntEn
18 r/w 0 TxDataLowIntEn
17 r/w 0 RxOverunIntEn
16 r/w 0 RxQ1LowBuffersInt
15 r/w 0 NormalInterruptEn
14 r/w 0 TxFrameCompleteIntEn
13 r/w 0 TxDmaDoneIntEn
12 r/w 0 TxQueueDoneIntEn
11 r/w 0 EarlyRxQ2IntEn
10 r/w 0 EarlyRxQ1Int
9 r/w 0 RxQ2DoneInt
8 r 0 RxQ1DoneInt
7 r/w 0 RxGfpNoResponseIntEn
6 r/w 0 RxQ2LowBuffersInt
5 r/w 0 NoTxChecksumIntEn
4 r/w 0 TxLowPrMismatchIntEn
3 r/w 0 TxHiPrMismatchIntEn
2 r/w 0 GfpRxIntEn
1 r/w 0 GfpTxIntEn
0 r/w 0 PCIPadIntEn