Technical information

7-37
Register Descriptions
Transmit Registers
TxDescQueueCtrl Register
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: 90h - 93h
Table 7-46. TxDescQueueCtrl Register
Bit(s) rw
Reset
Value Description/Function
31:24 r/w 2
TxHighPriorityFifoThreshold:
Specifies a programmable
threshold. When the transmit engine is transmitting data from a
frame that is currently being DMA-transferred (End-Of-Frame not
yet been fetched from host memory, and the number of transmit
data bytes stored in the FIFO drops below the threshold), the
transmit DMA engine asserts a high priority DMA request instead
of the normal priority one.
The internal BAC module arbitrates the receive and transmit DMA
requests, detects the request priority, and gives the transmit priority
over the receive.
The programmable threshold is defined in bytes as:
16*T
X
H
IGH
P
RIORITY
F
IFO
T
HRESHOLD
.
Note:
The
T
X
H
IGH
P
RIORITY
F
IFO
T
HRESHOLD
register must have
values less than or equal to the
T
X
T
HRESHOLD
register defined in
T
RANSMIT
F
RAME
C
TRL
register
.
23:21 r 0
Reserved:
Always written as 0.
20:16 r/w 0
SkipLength:
At the front of every frame/buffer transmit DMA
descriptor there is a field reserved for software driver usage. The
skip length field specifies that field size. The skip length is
(
SkipLength*8
) bytes. If the field is 0, the skip length is 0.
15:14 r 0
Reserved:
Always reads 0.
13:8 r/w 4
TxDmaBurstSize:
Specifies the number of bytes that the transmit
DMA engine requests from the PCI master during its host memory
access. Before issuing a new request, the transmit DMA engine
checks to see if there is enough room in the FIFO to store
(
T
X
D
MA
B
URST
S
IZE
*32)
bytes of data.
Note:
The transmit DMA engine can request the PCI master to fetch
more data than
T
X
D
MA
B
URST
S
IZE
*32
in order to align the DMA
address to next cacheline boundary if the number of bytes that
remains in the buffer is less than a cacheline. In addition, the
transmit DMA can request the PCI Master to fetch less data than the
burst size if the host buffer is smaller than the burst size.
7r/w0
TxDescQueue64bitAddr:
If set to a ‘1’, the transmit buffer
descriptor queue contains a 64-bit address. The AIC-6915 PCI
master must then use the 64-bit addressing mode to access the
queue. The high address is defined in the
T
X
D
ESC
Q
UEUE
H
IGH
A
DDR
register.