Technical information

7-44
AIC-6915 Ethernet LAN Controller Programmer’s Manual
RxCompletionQueue1Ctrl
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: BCh - BFh
4r/w0
CommonQueueMode:
When this bit is set, the receive completion
queues are disabled and all completion descriptors and general chip
status are DMA-transferred to the Transmit Completion Queue. This
bit overrides any values specified for the receive completion queues.
In this mode the maximum receive completion size is 8-bytes.
3:0 r/w 0
TxCompletionQueueThreshold
specifies a threshold equals to
4*T
X
C
OMPLETION
Q
UEUE
T
HRESHOLD
.
If
T
X
C
OMPLETION
T
HRESHOLD
M
ODE
is ‘0’ and the number of
empty
entries in transmit queue is less or equal to the threshold, an
interrupt status bit is set.
If
T
X
C
OMPLETION
T
HRESHOLD
M
ODE
is ‘1’ and the number of
valid
completion entries in transmit queue is greater than or equal to the
threshold, an interrupt status bit is set.
Table 7-57. RxCompletionQueue1Ctrl Register
Bit(s) rw
Reset
Value Description/Function
31:8 r/w x
RxCompletionQ1BaseAddress[31:8]:
This field contains the
starting address of the queue in host memory. It is written by the
host driver during initialization and read by the AIC-6915. The
amount of host memory allocated for the completion queue is either
4-KBytes, 8-KBytes, or 16-KBytes (programmable by bits 5:4,
R
X
C
OMPLETION
Q2T
YPE
). The starting address must be aligned to a
256-byte boundary.
7r/w0
RxCompletionQ1_64bitAddress:
The bit indicates if Receive
Completion Queue 1 is located in 64-bit address space. If so, the
AIC-6915 PCI master must use 64-bit addressing mode to access the
queue.
6r/w0
RxCompletionQ1ProducerWe:
When this bit is set, the software
driver is able to write the receive completion queue producer index.
Otherwise, writes to the index are disabled.
5:4 r/w 0
RxCompletionQ1Type[1:0]:
Controls the type of the completion
descriptor.
‘
00
’ - One word completion entry.
‘01’
- Two word completion entry. The second word contains
extended status and the VLAN ID and priority.
‘10’
- Two word completion entry. The second word contains a
partial checksum and 16 status bits.
‘11’
- Four word completion entry. The entry contains a
timestamp, full status, VLAN ID and priority, and the partial
checksum.
Table 7-56. TxCompletionQueueCtrl Register (Continued)
Bit(s) rw
Reset
Value Description/Function