Technical information

7-53
Register Descriptions
RxDescQueue2LowAddress
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: E4h - E7h
RxDescQueue1Ptrs
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: E8h - EBh
7:0 r 0
Reserved:
Always write 0
Table 7-67. RxDescQueue2LowAddress Register
Bit(s) rw
Reset
Value Description/Function
31:8 r/w
RxDescQ2LowAddress[31:8]:
This field indicates the 24 high-order
bits of a 32-bit address of the first Receive Buffer Descriptor Queue.
The lower 8 bits of the address must be 0. This field is written by
host driver during initialization and read by the AIC-6915 during a
receive DMA operation.
Note:
The address must be aligned to 256-byte boundary.
7:0 r 0
Reserved:
Always write 0
Table 7-68. RxDescQueue1Ptrs Register
Bit(s) rw
Reset
Value Description/Function
31:27 r/w 0
Reserved:
Always write zero.
26:16 r/w
RxDescQ1Consumer:
Written by the AIC-6915 and read by host.
This field indicates the address of the last descriptor read by the
AIC-6915. The software driver should use the
E
ND
I
NDEX
value in
the receive completion descriptor rather that this value to determine
which buffer the AIC-6915 has used because if the AIC-6915 receives
a bad frame, it reverts the consumer back to the beginning of the
frame to reuse the buffers. Software can write this field only after
setting the
R
X
Q1C
ONSUMER
W
E
bit in the
R
X
D
ESC
Q
UEUE
1C
TRL
register.
15:11 r/w 0
Reserved:
Always write 0.
10:0 r/w
RxDescQ1Producer:
Written by host driver and read by the
AIC-6915. This field indicates the index value after the last
descriptor.
Table 7-66. RxDescQueue1LowAddress Register (Continued)
Bit(s) rw
Reset
value Description/Function