Technical information

7-62
AIC-6915 Ethernet LAN Controller Programmer’s Manual
BacDmaDiagnostic0 Register
Type: R
Internal Registers Subgroup: PCI Extra Registers
Byte Address: 0110h - 0113h
BacDmaDiagnostic1 Register
Type: R
Internal Registers Subgroup: PCI Extra Registers
Byte Address: 0114h -0117h
This register provides information about the current DMA transfer, used for
diagnostic purpose only.
Table 7-77. BACDMADiagnostic0 Register
Bit(s) rw
Reset
Value Description/Function
31:29 r 0
Reserved:
Always read as 0.
28:16 r X
StartFifoPtr[12:0]:
This is a tri-state bus that contains the start value
of the FIFO pointer of the current DMA transfer. This value is driven
by the DMA requester and is stable until another DMA requester is
granted. This value is synchronized to the Ethernet clock.
15:12 r 0
Reserved:
Always read as 0.
11:0 r 0
PCITransferCount[11:0]:
This field is implemented in the BAC
module and contains the number of bytes transferred between
system memory and the transmit or receive FIFOs when the
AIC-6915 is an active bus master. The
PCITransferCount
field
functions as a counter that decrements by one each time a byte is
transferred between the PCI master and the FIFOs. Transfers are
inhibited when the count value of
TransferCount
is zero. This register
is used for diagnostic purposes only.
Table 7-78. BacDmaDiagnostic1 Register
Bit(s) rw
Reset
Value Description/Function
31:28 r 0
BacPCIState[3:0]:
Is the current state of BAC PCI state machine.
27 r 0
Reserved:
Always read as 0.
26 r 0
PCIDmaRead:
When set, the Data Path Direction bit indicates that
the data transfer is from the PCI bus (system memory) to one of the
FIFOs. Clearing the bit indicates that the data transfer is from the
FIFO to the PCI bus (system memory).
25:13 r 0
PCIFifoPtr[12:0]:
A byte address of the FIFO location currently being
read or written. The BAC module control the address which is synchro-
nized to the PCI clock.
12:0 r X
PCIFifoSpace[12:0]:
Represents the actual number of data bytes in the
FIFO during a DMA write operation, or the number of empty bytes in the
FIFO during a DMA read operation. This information is provided by the
BAC to the PCI master module during an active DMA transfer.