Technical information

7-80
AIC-6915 Ethernet LAN Controller Programmer’s Manual
MIIStatus Register
Type: R/W
Internal Registers Subgroup: MAC Registers
Byte Address: 5070h - 5073h
Table 7-106. MIIStatus Register
Bit(s) rw
Reset
value Description/Function
31:5 r 0
Reserved:
Always read as 0.
4r0
MIILink Fail:
MII Link Fail indicator. Setting this bit indicates to the
current PHY that the AIC-6915 is continuously scanning for link
status. The external PHY’s Status register’s (Register 1) bit 2, has
failed. This bit is cleared during normal operation.
Note:
This bit is only valid when the
S
CAN
bit is set. Otherwise, the
bit has no meaning.
3r0
NotValid:
Indicates the period of time at the beginning of a scan
operation when the external PHY link fail indicator (MIILF) is not
valid.
2r/w0
Scan:
MII management scan. When this bit is set, the host
continuously reads the same external
MII PHY
register specified by
MIIP
HY
A
D
and
MIIR
EG
A
D
in the MIIAdr register. The
MIIA
DR
register must be appropriately set before turning on this bit. The
intention use of this bit is to continuously monitor the ‘Link Status’
bit in
MII
register 1 (bit 2).
1r0
MiiDataValid:
MII management data valid. When the serial MII
management interface completes a read transaction from an external
physical device, the read data and the address of the device (as its
mapped in the AIC-6915) are latched, and the
M
II
D
ATA
V
ALID
bit is
set, indicating to the software driver that valid data is ready. Any
read or write to the
MIIR
EGISTERS
A
CCESS
P
ORT
resets the bit, unless
it is a read access, and the target address equals the latched address
of the read data. In this case
M
II
D
ATA
V
ALID
resets only after the
data is passed to the host, otherwise it resets immediately.
0r0
MiiBusy:
MII management busy. The host should poll this bit before
reading data from
MIIA
CCESS
P
ORT
register or issuing next write
command. It is high when MII serial interface is transferring data.