Technical information

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AIC-6915 Ethernet LAN Controller Programmer’s Manual
Features
General
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Supports four general purpose I/Os that can be programmed separately as inputs,
outputs, open-drain outputs or, interrupt inputs
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Interface to an external, 8-bit Boot ROM with a maximum size of 256-KByte
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Supports dynamic system bus (PCI) clock where the network can continue to
operate at any clock frequency
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Internal loopback on all network ports for testing purposes
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IEEE 1149.1 compliant JTAG Boundary Scan Test Access port
Ethernet
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IEEE 802.3 compliant 10/100 MII that supports Category 3 UTP, Category 5 UTP,
Type 1 STP and Fiber cables
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IEEE 802.3.x compliant Flow Control mechanism
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Supports Cisco proprietary VLAN ISL frame format
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Supports IEEE 802.1q (VLAN) frame format
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Supports PCI and OnNow power management
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Supports OnNow wakeup function
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Calculates TCP/IP checksum in transmit mode
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Checks TCP/IP checksum in receive mode
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Supports full-duplex operation on all ports (MII, 10/100 Twisted Pair)
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Provides a variety of address filtering modes:
–Promiscuous
– 16 full 48-bit addresses
– 512-bit hash table for multicast address filtering
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Time stamp information of every frame received
DMA
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Two transmit DMA queues to prioritize network traffic
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Enhanced interrupt mechanism increases performance and reduces CPU utilization:
– Transmit DMA Complete (Early Transmit)
–Early receive
– Transmit/Receive buffer under/over flow error handling. No software
intervention required
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DMA channel arbitration eliminates overrun/underrun of First-In-First-Out (FIFO)
buffers