Technical information

8-4
AIC-6915 Ethernet LAN Controller Programmer’s Manual
1 PCI
C
OMMAND
Register (offset 04h): The PCI Command register must be initialized
to enable memory and/or I/O register access, to enable bus master mode, to enable
Memory Write and Invalidate, and to enable system error response. The Command
register does not have to be reinitialized for a reset operation.
2 PCI
H
IGH
BASEADR0
Register (offset 14h): For 32-bit addressing, the upper 32 bits
of the memory address should be initialized to zero. This step does not have to be
repeated for a reset operation.
3 PHY Reset:
PHY
initialization in the sample driver is based on the Seeq Technology
Incorporated 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface
Adapter. The developer is referred to the Seeq data sheet for more information on
PHY operation. Following reset of the PHY, a delay of three seconds must be
observed in order to allow completion of the autonegotiation process and transmit
timing synchronization.
4
G
ENERAL
E
THERNET
C
TRL
Register (offset 70h): The driver must ensure that the chip
is not already enabled before beginning the initialization process. Writing a value of
0 to this register will disable receive and transmit DMA and the receive and transmit
engines.
5 PCI Device Configuration Register (offset 40h): Use this register to perform a
software reset and then to specify PCI interrupts. At a minimum the
I
NT
E
NABLE
bit
must be set. A two microsecond delay is required after this register is set.
6 PCI Status Register (offset 06h): The PCI Status register must be cleared at reset time,
to reset any error indications which may have been set. The Status register is cleared
by writing all 1’s to it.
7
M
AC
C
ONFIG
1
Register (offset 5000h): This register controls certain MAC
characteristics. The register must first be programmed to the desired settings. The
internal MAC must then be reset by setting the
M
AC
S
OFT
R
ST
bit. The
M
AC
S
OFT
R
ST
bit must then be cleared, and the register written again. Refer to the code sample
below for specific details.
Required Fields:
– FullDuplex: The driver should initialize the duplex mode after determining the
appropriate setting, either from an operating system configuration such as the NT
registry, or from a setting determined from autonegotiation. The BkToBk IPG
register setting may also need to be adjusted.
– MacSoftRst: This bit is set and then cleared in two separate write operations. This
is required to reset the internal MAC state after any control bits in this register
have been enabled.
After all other registers have been initialized, this register is written again to begin
the transmit and receive processes. The receive and transmit DMA operations must
be enabled, as well as the receive and transmit engines.
Required Fields:
– ReceiveEn = 1: Enable the receive engine.
– TransmitEn = 1: Enable the transmit engine.
– RxDmaEn = 1: Enable receive DMA.
– TxDmaEn = 1: Enable transmit DMA.