Technical information

1-4
AIC-6915 Ethernet LAN Controller Programmer’s Manual
– Memory Write And Invalidate
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Supports PCI bus address and data parity generation and checking
■
Supports PCI
PERR
and
SERR
requirements
■
Supports 8-bit, 256-KByte, external Memory port for interface with external Boot
ROM or devices/registers
■
Supports external Boot ROM access from memory or Expansion ROM address space
■
Supports an external serial EEPROM for downloading chip configurations and MAC
address
■
INTA_ interrupt generation from hardware, firmware, and software controlled
sources
■
Supports PCI slave accesses to PCI Configuration Header from configuration
(read/write), I/O (indirect, read only) and memory address spaces (read only)
■
Supports PCI slave access to AIC-6915 functional registers from configuration, I/O
and memory address spaces
■
Supports PCI slave access to AIC-6915 debug/buffer/FIFO Ethernet registers
(implemented in the Ethernet control module) and external Memory port from
indirect I/O and memory address spaces
■
PCI target latency of 16 clocks maximum for the first target access cycle. The
AIC-6915 initiates a cycle retry when an access requires more than 16 clocks to
complete