Technical information

1-5
Introduction
Block Diagram
Figure 1-1 is a block diagram of the AIC-6915.
8 KByte SRAM
Combined
Tx/Rx FIFO
PCI
BusAccessControl
SlaveAccess
, system registers
(
Slave)
(Master)
MAC
(
Transmit
)
(
Receive
)
Data (8)
Status
Status
(32 bits)
(64 bits)
PCI Bus (64-bits)
EPROM
Serial
Port
EPROM
DMA Bus (64-bits)
FIFO Bus (32-bits)
RxDMA
RxFrame
TxFrame
TxDMA
Station
Address
Data (8)
Control
Arbiter
Sync
.
PCI Clock
Comp
.
Receive Clock
Status
Statistics
TCP
Checksum
Wakeup
TCP
Checksum
Status
Receive Clock Domain
PCI Clock Domain
Transmit Clock Domain
Figure 1-1. AIC-6915 Block Diagram