Technical information

2-5
Receive Architecture
Accepting frames
The AIC-6915 uses two criteria when deciding whether to accept a frame: Frame address
and frame quality. When receiving a frame, the Station Address block evaluates a frame’s
address to determine if this station should receive the frame. Address filtering is
accomplished by the time 64bytes are received. During this time, the General Frame
Processor (GFP) also determines some characteristics about a frame, such as whether it is
a TCP frame, whether it should override the descriptor or completion queues used, and
the length of the header.
The MAC also determines some characteristics about the frame, such as its length, and
whether any errors have occurred. This evaluation completes by the end of the frame, and
the frame is assigned a “quality” based on this information. Normally, frames are only
accepted if there are no CRC errors, no extra nibbles or bits, and the length is legal (less
than or equal to a programmable value, normally 1536, and at least 64 bytes). However,
the following control bits can allow additional frames to be accepted:
■
RxDmaCrcErrorFrames - if set, accept frames with a CRC errors
■
RxDmaLongFrames - if set, frames longer than a programmable value (normally
1536) are accepted. Otherwise, they are rejected
■
RxDmaBadFrames - if set, accept frames with a CRC error, nibble or code violation
■
RxDmaShortFrames - if set, the AIC-6915 accepts frames shorter than 64 bytes.
■
RxReportBadFrames - if set, the AIC-6915 reports the status for long and bad frames
to the host, although it reuses the buffers for the next frame. Otherwise, the AIC-6915
does not report any status when it receives a bad frame, but only updates internal
statistics.
Once 64 bytes of a frame have been received successfully, the AIC-6915 can start DMA-
transferring the frame to the host. In some operating modes, such as header splitting, it
must also wait for the frame processor to process the frame’s IP header. If the frame is bad,
the AIC-6915 does not inform the host of the buffers it used for that frame. Rather, it backs
up its internal pointers and reuses those buffers on the next frame. The receive DMA
engine transfers the receive data in amounts equal to the RxBurstSize field specified in
RxDmaCtrl register. The DMA operation starts when a number of bytes equal to or greater
than RxBurstSize is stored in the FIFO. When the number of bytes in the FIFO exceeds a
programmable threshold (RxHighPriorityThreshold), the receive DMA engine is granted
priority over the transmit engine for DMA services.
Completion Descriptor
A completion descriptor is normally DMA-transferred to the host when a good frame is
received. The frame is DMA-transferred to the host and indicates the frame status, frame
length, and the number of buffers used.
Various formats of completion descriptors are available, with RxCompletionQ1Type
selecting the type to use the main completion queue, and RxCompletionQ2Type selecting
the type to use in the high-priority queue.
If RxCompletionSize is set, the completion descriptor includes only the first word shown.
If the bit is cleared, the first two words are shown. The RxCompletionType field controls
whether the second word contains the TimeStamp, data from the Frame Processor, or some
frame processor data and the VLAN ID.
A valid completion descriptor will never have a length field with a value of 0.