Technical information

3-7
Transmit Architecture
■
INTR
: Causes setting of the interrupt status bits (TxDmaDoneInt and/or
TxFrameCompleteInt) after complete transmission of the entire packet. The
appropriate interrupt status bit is set based on two control bits that the software
programs at the initialization phase. Given ‘
INTR’ is set the following table specifies
the functionality:
Note:
The software driver may choose to work with another interrupt status bit,
TxQueueDoneInt, that is not controlled by ‘
INTR’. The AIC-6915 sets this bit after
the DMA-transfer of a completion descriptor for the last frame queued for
transmit. The last frame is detected when the consumer and producer indices of
the queue are equal.
■
CRCEN
: Setting this bit enables the MAC to calculate and append the CRC value for
the current packet. Clearing the bit disables the MACs ability to calculate the CRC
value.
■
CALTCP
: Setting this bit enables the F P to calculate TCP/UDP checksum for this
packet. Clearing the bit disables the FPs ability to calculate the checksum.
Table 3-2. End Bit Functionality
Desc. Type Conditions Functionality
Frame (0,3,4) MinFrameDescSpacing
!=0
The number of bytes between two
consecutive frame descriptions is fixed. The
queue wraps around at the end of the fixed
address. No wrap in the middle of a frame
descriptor.
Frame (0,3,4) MinFrameDescSpacing
=0
The number of bytes between two
consecutive frame descriptions is variable.
For type 0/4, the queue wraps after reading
16 bytes of descriptor data. For type 1/3, the
queue wraps after reading 8 bytes of
descriptors.
Buffer (1,2) MinFrameDescSpacing
must be 0.
‘End’ bit is valid only
for the first descriptor
of a frame.
For type 1, the queue wraps after reading 8
bytes of descriptors data.
For type 2, the queue wraps after reading 16
bytes of descriptor data.
Table 3-3. Intr Bit Functionality
DisableTxDmaCo
mpletion
TxCompletionDescAft
erTxComplete Functionality
0 0 TxDmaDoneInt is set after complete DMA the
whole packet.
0 1 TxDmaDoneInt is set after complete DMA the
whole packet, and TxFrameCompleteInt is set
after complete transmitting the whole frame.
1 0 None of the two interrupt status bits is set.
1 1 TxFrameCompleteInt is set after complete
transmitting the whole frame. ‘INTR’