Technical information

4-1
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PCI Module Architecture
Features
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Compliant with PCI Local Bus Specification, Revision 2.1
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Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00
and Microsoft Device Class Power Management Reference Specification (OnNow)
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PC 97 ready. Implements all hardware features required by Microsoft’s PC 97 design
specification
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Supports 3.3V and 5.0V PCI signaling
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Direct pin out connection to PCI 32/64-bit bus interface
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PCI bus master with zero wait state 32/64-bit memory data transfers at 133/266
MBytes/sec, capable of supporting leading and trailing byte offset for DMA read
and write (32-bit) for DMA write.
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Supports PCI Single/Dual address cycles in target mode and Single/Dual address
cycles in master mode.
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PCI bus master/slave timing referenced to PCI signal PCLK (33.3 MHz max)
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PCI bus master programmable Latency Timer, Cache Size, and Interrupt Line Select
registers
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Supports cache line sizes of 4, 8, 16, 32, and 64 words
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Supports any combination of active byte enables for all PCI slave accesses
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Supports medium PCI target device-select response time
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Supports, as a bus master, enhanced PCI System memory data read and write
commands:
– Memory Read
– Memory Read Line
– Memory Read Multiple
– Memory Write
– Memory Write And Invalidate
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Supports PCI bus address and data parity generation and checking.