Technical information

4-2
AIC-6915 Ethernet LAN Controller Programmer’s Manual
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Supports PCI PERR and SERR requirements.
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Supports 8-bit, 256-KByte, external Memory port for interface with external Boot
ROM or devices/registers.
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Supports external Boot ROM access from memory or Expansion ROM address space.
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Supports an external I
2
C serial EEPROM for downloading chip configurations and
MAC address.
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Optional external serial EEPROM support for downloading PCI Configuration
information and CardBus (Card Information Structure, CIS) pointer when a PCI
hard reset is applied.
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INTA_ interrupt generation from hardware, firmware, and software controlled
sources.
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Supports PCI slave accesses to PCI Configuration Header from configuration
(read/write), I/O (indirect, read only) and memory address spaces (read only).
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Supports PCI slave access to AIC-6915 functional registers from configuration, I/O
and memory address spaces.
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Supports PCI slave access to AIC-6915 debug/buffer/FIFO Ethernet registers
(implemented in the Ethernet control module) and external Memory port from I/O
(indirect) and memory address space.
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PCI target latency of 16 clocks maximum for the first target access cycle (revision 2.1
support). The AIC-6915 initiates a cycle retry when an access requires more than 16
clocks to complete.