Technical information

4-4
AIC-6915 Ethernet LAN Controller Programmer’s Manual
PCI Master Module
The PCI master transfers data to/from system memory. Therefore, the AIC-6915 never
generates PCI transactions for Interrupt Acknowledge, Special Cycle, I/O space, or
Configuration space. The PCI master generates all Memory space commands, and uses
the optional ones as appropriate to make efficient use of cache-oriented memory
hardware.
The module transfers a minimum 32-bits of data per Data phase, even if it has to fetch
(DMA read) less than that. The selection of the right bytes and the byte alignment
operation is done internally in the BAC module.
Note:
In case of a DMA write the data must always be aligned on a 32-bit
boundary.
The PCI master has a programmable option to assert only the byte enables corresponding
to data it has to fetch. This option can be used in systems where reading extra bytes might
cause a problem.
The PCI master module samples
DEVSEL_ when initiating a transaction to a selected
target in order to determine if the target is capable of proceeding with the current
transaction. In the case when
DEVSEL_ is not asserted by the selected target for five
PCLKs (SAC - single address cycle) or six
PCLK
S
(DAC - dual address cycle) after FRAME_
is asserted, the AIC-6915 performs a master-abort.
The PCI master does not retry transactions that resulted in a master-abort (no response
from target) and generates an interrupt to the driver with the RMA (Received Master
Abort in the PCI Configuration Status register) status active. Intervention by the software
driver is required for the AIC-6915 to continue with bus master transactions.
The PCI master does not retry transactions that resulted in a target-abort and generates an
interrupt to the driver with RTA (Received Target Abort in the PCI Configuration Status
register) status active. Intervention by the software driver is required for the AIC-6915 to
continue with bus master transactions.
The PCI master detects and reports parity errors. In normal operation mode, the AIC-6915
continues the DMA transfer even if a parity error is detected. The software driver can
request the AIC-6915 to stop the DMA transfer when a parity error is detected and
suspend any other DMA operations until the error is serviced.
The PCI master is designed to burst data as much as possible. Whenever it starts a burst
transfer, it continues until one of the following conditions occurs:
■
The target disconnects or aborts.
■
A Parity error is detected and the StopOnParErr bit is set.
■
The DMA counter expires (all requested data has been transferred).
■
The GNT_ signal is deasserted and the Latency timer expires.
■
The AIC-6915 never asserts wait states (‘irdy_’ is always ‘1’) and completes the
transfer even if it detects that there is no data or room in the FIFO.