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4-5

PCI Module Architecture

64-bit PCI Bus Master

The AIC-6915 supports a 64-bit PCI bus master and performs 64-bit data transfers with a

64-bit target. If the responding target is a 32-bit device, the lower 32-bit of address bus is

used.

The

REQ64_ signal is used to determine whether the system supports a 64-bit data path. A

pull-up resistor on the motherboard places the PCI bus in 32-bit mode by default. For PCI

expansion cards that do not support 64-bit PCI data path, the

REQ64_ must be pulled-up

with a separate pull-up resistor. The central resource must assert

REQ64_ during the time

that

RST_ is asserted, according to the timing specification.

Sixty-four bit data transfer capability is only supported for memory commands. When the

PCI bus master starts a transfer and

REQ64_ is asserted, the starting address is

doubleword aligned. This means that

AD[2:0] must be set to zero. The AIC-6915 issues a

64-bit data transfer instead of a 32-bit data transfer by the number of bytes transferred and

the starting address: hcnt >= 16 bytes and DmaAddr[2:0] = 0, for simplicity of

modifications. The 64-bit address alignment (DmaAddr[2:0] = 0) requirement is removed

and the AIC-6915 issues a 64-bit transfer for any starting address.

Upon request from the Ethernet control module for a PCI transfer, the PCI master

determines whether to use a 64-bit or a 32-bit transfer according to the above conditions.

For a 64-bit data transfer, the PCI master asserts

FRAME_ and REQ64_ to indicate the start

of a 64-bit data transfer, then waits for the target device to assert

DEVSEL_ to claim the

transaction and check whether

ACK64_ is asserted. If ACK64_ is asserted, the PCI master

starts a 64-bit data transfer. If not, a 32-bit data transfer is performed.

If a multiple data transaction cycle is being disconnected after the first 32-bit transfer, the

AIC-6915 restarts the transaction with a 32-bit transfer. Under this situation, it is very

possible that the target is a 32-bit device and does not support multiple-data transfer

cycles. If the master continues with the 64-bit data transfer cycle, the lower 32-bit data

byte enables are deasserted and no data is transferred before the target initiates a

disconnect again. Therefore, the upper 32-bits of data can never be transferred.

Pci Clk

RST_

REQ64_

REQ64_ to RST_

setup min

Figure 4-2. 64-bit PCI Reset Timing

hold time

RST_ to REQ64_0 ns to 50 ns

cycle time