Technical information

4-6

AIC-6915 Ethernet LAN Controller Programmer’s Manual

Arbitration

The AIC-6915 drives AD[31:00] during 32-bit transfers and AD[63:0] during 64-bit transfers.

CBE[3:0]_ are asserted on the first PCLK when GNT_ is sampled asserted and the PCI bus

idle.

PAR and PAR64 are asserted one PCLK later. The AIC-6915 also asserts FRAME_ and

REQ64_ for 64-bit transfers if PREQ_ is asserted to start a DMA transfer. The assertion of

PREQ_ indicates to the PCI System board arbiter that a master desires use of the bus. When

a transaction is terminated by a target, the master must deassert its PREQ_ signal for a

minimum of 2 PCLK periods (one period must include the bus idle period). This allows

another agent to use the bus while the previous target (that requested the STOP) prepares

to continue.

Note:

This is not required where the master deasserted FRAME_, indicating the

last data phase of a transaction is in process. In this case, provided

GNT_ is still

asserted, the master could start another transaction without deasserting PREQ_.

PCI Target Module

The AIC-6915 uses Base Address 0 to request that the system allocate 512 K Bytes of

memory space. Base Address 1 is used to request that the system allocate 256 bytes of I/O

space. The AIC-6915 uses the expansion ROM base address to request from the system to

allocate 256 KBytes of memory space to access an External ROM.

When the AIC-6915 detects a PCI cycle which is addressed to it, it checks the command to

verify that it can respond, then asserts

DEVSEL_ with medium speed. As a target device,

the AIC-6915 distinguishes between cycles targeted to registers implemented in the PCI

clock domain, and other registers implemented in the Ethernet clock domain which can be

also implemented externally. When the cycle is targeted to a register in the Ethernet clock

domain, the PCI target asserts a request to the module to complete the cycle, then waits

for it to acknowledge before terminating the transaction on the PCI bus.

The AIC-6915 issues a target retry if more than 16 PCI clocks are required to terminate the

cycle. Retry is an operation on the PCI bus that occurs when an external bus master

accesses the AIC-6915 (AIC-6915 is the target). If the target is not ready, it responds with a

cycle retry indication on the PCI bus. PCI module asserts the signal

RETRY to indicate that

the cycle cannot be completed within 16 PCI clock cycles. When the target samples the

RETRY signal and is asserted, it terminates the PCI cycle. Target retry can happen only if

the cycle is targeted to a register implemented in the Ethernet clock domain, or to the

serial EPROM at boot time (after hard reset), if selecting nondefault values for the PCI

configuration header registers.

The posted write function is used when the AIC-6915 is being targeted to access any

Ethernet clock domain registers. The PCI module captures the target address and byte

enables to its internal registers and completes the slave access. However, it will not accept

any slave accesses until the current write is being completed by the Ethernet

LOCK

OMAIN