Technical information

4-7
PCI Module Architecture
The value of BR_A1 pin is sampled when PCI reset is active to determine if the serial
EPROM data (
BR_A1=1) or the default values (BR_A1=0) should be used for
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Vendor ID [7:0]
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Vendor ID [15:8]
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Device ID [7:0]
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Device ID [15:8]
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Sub Class [7:0]
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Base Class [7:0]
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SubSystem Vendor ID [7:0]
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SubSystem Vendor ID [15:8]
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SubSystem Device ID [7:0]
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SubSystem Device ID [15:8]
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Interrupt Pin [7:0]
The target does not support data bursts. Rather it disconnects after the first Data phase. In
addition, the AIC-6915 does not support 64-bit target mode data transfers. Two locations
in I/O space are used as Data (IndirectIoDataPort) and Address (IndirectIoAddress)
registers. The Address register points to a word location within the 512K Byte memory
address space. When the target decodes and checks the legality of an access to its Data
register it selects the address stored in IndirectIoAddress as an input to its address
decoder and performs a read/write cycle using the address stored in IndirectIoAddress.
The target responds to such a cycle with the exact same behavior (checks legality of the
cycle) as if the master had initiated the transaction, executing a memory access with the
address stored in IndirectIoAddress. The target increments IndirectIoAddress if the cycle
completed successfully.
BE_[3] and EnIncrement (Enable Increment in PciDeviceConfig
register) are asserted. All 256 bytes are accessible directly in I/O space.
When the target detects a cycle to its I/O space, it checks that
CBE_[3:0] matches the
address. If the address does not match the cycle is aborted. The target receives and
executes a NOP cycle if none of the
CBE_ bits are asserted.