Technical information

4-9
PCI Module Architecture
CardBus
CardBus is the interface between a PC card and a portable device which has 32-bit bus
mastering capability. The CardBus interface is based on the PCI interface with lower power
consumption, additional signals and registers supported. There are four 32-bit CardBus
registers. The following events must be implemented:
■
Function Event
■
Function Event Mask
■
Function Present State
■
Function Force Event
An additional signal,
CLKRUN_ is used to maintain or start the PCI clock any time a card
wishes to start a PCI transaction. It is asserted low for two cycles after being sampled high
(not asserted) for two cycles. In the AIC-6915,
CLKRUN_ is asserted if any DMA request or
interrupt request is asserted, and
CLKRUN_ has been sampled high for at least two cycles.
When
CLKRUN_ is not asserted, the system is free to slow down or stop the PCI bus.
Retry Function
When a master is trying to access the EEPROM, Memory port interface and Ethernet clock
domain in the AIC-6915, the retry functional block determines whether the transaction
can be completed within 16 clock cycles. If the access cannot be completed within 16 clock
cycles, the target address and byte enables are stored in the PCI module while a retry is
issued by the master. Once a retry is signalled, no other PCI slave access can be accepted
until the current slave access is completed by the same master (for read) or the current
data has been completed (for write). The PCI module keeps signalling to the originating
master every time it requests until it has completed the access or until the timer expires
after 32768 PCI clock cycles.
Response to PCI Commands
The AIC-6915 does not contain cache memory, and the Memory Interface bus gains no
special efficiency from cacheline-size bursts, so the AIC-6915’s PCI target responds to the
cache-oriented memory space commands (Memory Read Multiple, Memory Read Line,
Memory Write and Invalidate) as if they were simple Memory Read or Memory Write
commands.
Any device on the External Memory Interface bus is accessible in PCI memory space or
I/O space using an indirect address which is stored in IndirectIoAddress register.
The PCI configuration header registers are accessible in configuration space and, as read
only, in memory, or I/O space (indirect).
The PCI Device registers are accessible in configuration, memory and I/O space (indirect).
The Ethernet control module registers (in the Ethernet clock domain) are accessible in PCI
memory and I/O space (indirect).
The IndirectIoDataPort and IndirectIoAddress are accessed only in I/O space (direct).
As a target, the AIC-6915 ignores Interrupt Acknowledge, Special Cycle, Dual Address
Cycle and Reserved commands. However, even for these commands, the address/
CBE_
parity-checking hardware remains active.