Technical information

5-1
5
▼▼▼▼
Frame Processor Architecture
Features
■
Calculate the TCP and UDP checksum
■
Decode frame type (TCP, UDP, ARP, RARP, IPX, Wake-up, VLAN 802.1q, Ipv4, Ipv6,
ICMP, Ethernet 2, IEEE 802/803)
■
Process Ethernet 2, 802, IPv4, IPv6, TCP and UDP headers
■
Process receive data on-the-fly. The maximum receive buffer requirement is 8-bytes
■
Same architecture for both transmit and receive
■
Ease of implementation, simple decoding logic, no pipeline, fixed instruction format,
simple commands
■
Maximum clock frequency is 25 Mhz. Cycle time of 40 nS is enough to read the
instruction RAM and execute the command without any critical pass.
■
16 bit data interface. Frame data halfword is sampled when DataValid is asserted
■
Provides indication when User Data field starts after UDP or TCP headers
■
Provides partial checksum result for fragmented TCP frame
General Architecture & Operation
When
D
ATA
V
ALID
is asserted, a new 16-bit halfword is read by the processor on the rising
edge of clock. The processor has an option to throttle down the data rate by deasserting
the signal
R
EQ
N
EXT
D
ATA
. New data can be presented to the processor only when
R
EQ
N
EXT
D
ATA
is sampled asserted. The interface between the processor and the receive
block does not take advantage of that option (
R
EQ
N
EXT
D
ATA
is asserted all the time) and
assumes that there are at list three instructions the processor can execute between two
consecutive assertions of
D
ATA
V
ALID
. In the interface with the transmit DMA engine, a
64-bit doubleword is read from the transmit FIFO and 16-bits are presented when
ReqNextData
is sampled asserted.
The processor reads and executes instructions from the instruction memory in 1 clock
cycle. The processor executes the instruction and jumps to the next address at the same
clock edge if
■
Loop Counter (LC) is: ‘0’ ‘1’ or ‘2’, and
D
ATA
V
ALID
is set, or