Technical information

5-2
AIC-6915 Ethernet LAN Controller Programmer’s Manual
■
LC= 0, 1 or 2, and
E
XC
O
N
C
LOCK
is set, or
■
Read/Write instruction is executed and the Input
IOR
EADY
is sampled asserted.
Note: E
XC
O
N
C
LOCK
is a bit in the instruction.
The loop counter is decremented by 2 every clock cycle if
E
XC
O
N
C
LOCK
=1, or if
D
ATA
V
ALID
is asserted. The loop counter stops when reaching its terminal count of zero.
Decrementing the counter by 2 each time assures that incoming data is on a byte
boundary.
The processor writes 16-bit data (ALU output) to a 16-bit address space defined in the
instruction. It can also read a location pointed by an address defined in the instruction,
and load the data to any of its working registers. The data read is passing through the
ALU and can also be processed if specified by the instruction.
Wake-up Mode
When the chip is functioning in power down mode, the GFP is loaded with a program
designed for decoding wake-up frames. When the GFP decodes a wake-up frame it
asserts the status bits
W
AKEUP
F
RAME
and
G
FP
D
ONE
. External logic is responsible to
execute all the processes required by Microsoft On-Now specification, including assertion
of the
PME_
signal.
When working in wake-up mode, the GFP should not be reset between frames. Instead
the input
S
TART
O
F
F
RAME
is asserted to signal the beginning of a new incoming Ethernet
frame. This feature enables the GFP to try and decode multiple frame types in a serial
manner.
Transmit Checksum Accelerator
To accelerate the checksum calculation the 25 MHz clock must be connected to the GFP at
all times. When the GFP is ready to process the frame in a loop, it asserts the
S
TART
U
SER
D
ATA
status bit. At this point the transmit DMA engine presents (instead of
the regular frame data) a sum of two or more (up to four) 16-bit halfwords that are
computed in parallel (at one clock cycle), with an indication (
G
FP
B
YTE
C
NT
[3:0]
) of how
many bytes of frame data are included in the sum. The GFP then decrements the LC by
the number given by the transmit DMA engine. The maximum number is 8 = 2*4 and the
minimum number is three. The GFP implements a 16-bit frame counter,
GfpFrameCnt[15:0], which counts the number of
G
FP
D
ATA
V
ALID
from the beginning of
the Ethernet frame. The Transmit DMA engine monitors the counters 3 least significant
bits and activates the accelerator only when they are ‘0’. This guarantees that the
accelerator is activated only when 8 bytes of data is read from the transmit FIFO.
The transmit DMA engine must monitor
LC[15:0]
to detect when the number of bytes still
requiring processing is below 3, at which time the accelerator hardware is disconnected
from the data path. When the transmit DMA engine presents a sum of 2 or more
halfwords instead of the regular frame data, it must also provide 2 bits of carry
information (
G
FP
D
ATA
I
N
[17:16]
).
The transmit DMA engine can monitor the status register bits all the time since these are
available as outputs also. If it can be guaranteed that the TCP/UDP Checksum field is
presented as 0 x 0 to the GFP, then a few instructions can be saved.