Technical information

5-5
Frame Processor Architecture
Block Diagram
Figure 5-1 is a block diagram of the Data Processing Unit.
WR2[15:0]
8 Input Mux
Barrel Shifter
WR3[15:0]
Simple ALU:
Mask Control
Adder,
Comparator
ALU-Out[31:0]
Instruction
Loop Counter
WR1 WR2 WR3 WR4 LC
Input1 Input2
WR1[31:0] WR4[15:0]
Flag
8 Input Mux
Branch Logic
Instruction Ptr
(LC[15:0])
Frame Data
Data
BranchAdd
Data
Instruction
Memory
Register
IP
Immediate
Mask Control
Frame Data Counter
DataValid
Figure 5-1. Data Processing Unit