Technical information

5-9
Frame Processor Architecture
❒
MuxSelInput1 [29:17] Controls the 8 input mux operation at ALU input 1
‘
0
’ - Data
‘
1
’ - WR1[15:0]
‘
2
’ - WR2
‘
3
’ - WR3
‘
4
’ - Status[31:16]
‘
5
’ - Status[15:0]
‘
6
’ - FrameCnt
‘
7
’ - WR1[31:15]
AluCtrl [23:20] ‘
0
’ - NOP (Output=Input2, Flag=False)
‘
1
’ - ADD (Input1+Input2)
‘
2
’ - Check for Equality (Input1=Input2)
‘
3
’ - Check for greater than (Input1>Input2)
‘
4
’ - Check for greater than or equal (Input1>=Input2)
‘
5
’ - OR (Input1 | Input2)
‘
6
’ - AND (Input1 & Input2)
‘
7
’ - XOR (Input1 ^ Input2)
‘
8
’ - Invert (~Input2)
‘
9
’ - AddLong ({Wreg1[31:16],Input1} + Input2)
‘
A
’ - Decrement2 (Input1 - Input2)
‘
B
’ - Decrement1 (Input2 - Input1)
‘15’-’12’ - Reserved
BranchAdd [31:24] When the Opcode is a Branch to immediate command, then
BranchAdd points to the next instruction memory location. If the
command is Read/Write it indicates the target address.
Data [47:32] General data 1 field. Data is also a control field for the barrel shifter
and the Loop Counter.
If BarrelShifterCtrl=1 then:
Data[15] - If ‘0’ shift right, else shift Left.
Data[14:11] - Shift size.
if LoadLC=1 then:
Data[10] - Defines the operation mode of LC. If it’s set, LC is
loaded with a specified number, else LC is loaded with double the
specified number.
Note, LC is decremented by 2 every time an instruction is
executed.
Data[9] - If ‘0’ decrement LC every DataValid, else every clock.
Data[8] - When the bit is set and executing an instruction in a loop
and
ReqNextData
is asserted, then
ReqNextData
is cleared when
executing the last instruction in the loop.
Data[7] - Load Immediate data to LC.
Data[6] - Load ALU out to LC.
Data[5] - Load WR1 to LC.
Data[4] - Load WR2 to LC.
Data[3] - Load WR3 to LC.
Data[2] - Load WR4 to LC.
Table 5-2. Instruction Formats (Continued)
Name Bit Number Description