Technical information

6-1
6
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AIC-6915 Internal Registers
Summary
For the following registers, the ‘Byte Address’ indicates each registers location in memory
space given as a byte offset address from the start of the memory space dedicated for
internal registers - 0x50000h.
PCI Configuration Header Registers Summary
The PCI configuration registers are mapped to Memory Base Address+0x50000 in
memory space, 0x00 in configuration spaces and address 0x00 in I/O space. Each register
can be accessed on a read using Memory, I/O and configuration commands. Write
operations are limited to configuration commands only.
Table 6-1. PCI Configuration Header Registers Summary
Byte Addr Data Byte 3 Data Byte 2 Data Byte 1 Data byte 0
0000h Device ID Vendor ID
0004h Status Command
0008h Base Class Sub Class Program IF Revision ID
000Ch Built-In Self Test Header Type Latency Timer Cache Line Size
0010h LowBaseAdr0 (512-KByte Memory Space, low address bits)
0014h HighBaseAdr0 (high address bits)
0018h BaseAdr1 (256 byte I/O Space)
001Ch:0024h Reserved
0028h Card Bus CIS Pointer
002Ch SubSystem ID SubSystem Vendor ID
0030h Expansion ROM Control
0034h Reserved Cap_Ptr
0038h Reserved
003Ch Max Latency Min Gnt Interrupt Pin Interrupt Line