Technical information

7-6
AIC-6915 Ethernet LAN Controller Programmer’s Manual
PCI Command Register
Type: R/W
Internal Registers Subgroup: PCI Configuration Header
Byte Address: 04h - 05h
Table 7-5. PCI Command Register
Bit(s) rw
Reset
Value Description/Function
15:10 r 0 Always read as 0.
9r 0
MFBTBEN:
Master Fast Back-To-Back Enable. When active (=1)
indicates a master can perform Fast Back-To Back transactions to
different PCI targets. The AIC-6915 does not support this feature
and
MFBTBEN
always reads zero.
8r/w 0
SERRESPEN:
System Error Response Enable. When both
SERRESPEN
and
PERRESPEN
are set, the output
PCI_SERR_
can be asserted. As a target, the AIC-6915 only asserts
PCI_SERR_
for detected address parity errors.
SERRESPEN
is cleared during
and after assertion of
PCI_PCIRST_
.
7r 0
WAITCTLEN:
Always reads zero. The AIC-6915 does not support
Address/Data stepping.
6r/w 0
PERRESPEN:
Parity Error Response Enable. Setting this bit
enables
PCI_PERR_
to be asserted when a PCI 36-bit even parity
error is detected during the data phase of a transaction. The
AIC-6915 asserts
PCI_PERR_
when
PERRESPEN
is active and a
data parity error is detected as a target for write accesses or as a
master for read commands.
PERRESPEN
is set inactive during
and after assertion of
PCI_PCIRST_
.
5r 0
VSNOOPEN:
VGA Snoop Enable, Always reads 0. The AIC-6915
does not support
VSNOOPEN
.
4r/w 0
MWRICEN:
Memory Write and Invalidate Enable. Setting this bit
enables a PCI master to issue Memory Write and Invalidate
commands to more optimally transfer data to System memory.
When inactive the Memory Write and Invalidate command is
replaced with a Memory Write command.
MWRICEN
is set
inactive during and after assertion of
PCI_PCIRST_
3r 0
SPCYCEN:
Always reads as 0. Setting this bit allows a target to
monitor special cycle transactions broadcast on the PCI bus. The
AIC-6915 does not support special cycles as a target or master.
2r/w 0
MASTEREN:
Master Enable. Setting this bit enables the AIC-6915
to perform bus master transactions on the PCI bus. Note,
additional transactions to the AIC-6915's Device registers must be
performed before the AIC-6915 may request to be a bus master.
When inactive the AIC-6915 bus master transactions are inhibited.
MASTEREN
is set inactive during and after assertion of
PCI_PCIRST_
1r/w 0
MSPACEEN:
Memory Space Enable. Setting this bit enables the
AIC-6915 to respond to PCI memory space transactions. When
MSPACEEN
is inactive the AIC-6915 does not respond to PCI
memory space transactions.
MSPACEEN
is set inactive during
and after assertion of
PCI_PCIRST_