Technical information

7-14
AIC-6915 Ethernet LAN Controller Programmer’s Manual
PCI CapPtr (Capabilities List Pointer) Register
Type: R/W
Internal Registers Subgroup: PCI Configuration Header
Byte Address: 34h
PCI INTLINSEL (Interrupt Line Select) Register
Type: R/W
Byte Address: 3Ch
Table 7-21. Expansion ROM Control Register
Bit(s) rw
Reset
Value Description/Function
31:18 r/w 0
EXPROMCTL[31:18]:
Indicates the mapping increment capability
of 256-KBytes.
17:11 r 0
EXPROMCTL[17:11]:
Always read as 0. Set the maximum ROM
size to 256-KBytes.
10:1 r 0
EXPROMCTL[10:1]:
Reserved: Always read as 0.
0r/w0
EXPROMCTL[0]:
External ROM Enable. When this bit is set along
with the MSPACEEN bit in the Configuration Command register,
this bit enables the device to accept accesses to expansion ROM.
Unless both
EXROMEN
and
MSPACEEN
are active, accesses to
External ROM addresses do not return
PCI_DEVSEL_
and are
ignored.
Table 7-22. Capabilities List Pointer Register
Bit(s) rw
Reset
Value Description/Function
7:0 r 50’h
CapPtr[7:0]:
A pointer to the location of the first item in the New
Capabilities Linked List.
Table 7-23. Interrupt Line Select Register
Bit(s) rw
Reset
Value Description/Function
7:0 r/w 0
INTLS[7:0]:
Interrupt Line Select [7:0] is read-write register in
which the HOST can store information about the interrupt line
connected to the device. The PCI bus supports four interrupt lines
(INTA[D:A]
).