Technical information

7-18
AIC-6915 Ethernet LAN Controller Programmer’s Manual
18:16 r/w 000
EpromCsWidth:
Indicates the width of the EPROM chip-select.
‘000’ - 8 PCI clocks
‘111’ - 7 PCI clocks
‘110’ - 6 PCI clocks
‘101’ - 5 PCI clocks
‘100’ - 4 PCI clocks
‘011’ - 3 PCI clocks
All other combinations are reserved.
15 r/w 0
EnBeLogic:
When this bit is set and a DMA read is active, the PCI
master asserts leading and trailing data byte enables as a function of
DMA address and transfer size. When the bit is reset, the PCI master
always asserts all 4-byte enables for reading data from HOST
memory.
14 r/w 0
LatencyStopOnCacheLine:
When the latency timer expires and the
PCI grant is deasserted, the PCI master must stop the DMA transfer.
If the bit is set and a cache reference DMA Read command is
executed, the PCI master stops the DMA on the next cacheline
boundary, otherwise its stops immediately.
13 r/w 1
PCIMstDmaEn:
Enables the PCI master operation. The bit is cleared
when a DMA error, such as when
StopOnPerr
is asserted, or when a
master abort or target abort is detected during an active DMA
transfer.
To enable the PCI master operation the software must make sure
that;
PCIM
ST
D
MA
E
N
is set.
MASTEREN
is set (PCI Command register).
ISPACEEN
or
MSPACEEN
is set (PCI Command register).
12 r/w 0
StopOnCachelineEn:
When set, the AIC-6915 stops any memory
write or memory write and invalidate on a cacheline. Otherwise it
allows the target to control cycle termination.
11:8 r/w 1h
FifoThreshold[3:0]:
Specifies a value in a resolution of 16 bytes. This
value is used as a threshold to determine when the PCI master
should request the PCI bus. During an active DMA read operation,
the threshold is the number of data bytes stored in the FIFO. During
an active DMA write operation, the threshold specifies the amount
of room in the FIFO.
F
IFO
T
HRESHOLD
= 0 specifies a threshold of 256
bytes. The software driver should always use the default.
7r/w0
MemRdCmdEn:
Controls when the PCI master uses the simple
Memory Read command. If
M
EM
R
D
C
MD
E
N
is asserted, the
memory read command is used for all DMA read operations,
otherwise, memory read is used only when reading a number of
bytes that is less than or equal to four. A memory read line is used
for reading data up to the next cacheline, and a memory read
multiple is used if the read operation crosses a cache line boundary.
Table 7-27. PCIDeviceConfig Register (Continued)
Bit(s) rw
Reset
Value Description/Function